Santanu Sarkar
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Known people with the same name:
- Santanu Sarkar 001 (Indian Institute of Technology Madras, Chennai, India)
- Santanu Sarkar 002 (Indian Institute of Technology, Kharagpur, India)
Bibliography
2024
Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique.
Int. J. Circuit Theory Appl., May, 2024
An 8-bit 1 MS/s Low-Power SAR ADC with an Enhanced EPC for Implantable Medical Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
IACR Cryptol. ePrint Arch., 2023
2022
Risk Analysis of Green Supply Chain Using a Hybrid Multi-Criteria Decision Model: Evidence from Laptop Manufacturer Industry.
Axioms, 2022
2020
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016