Santanu Sarkar

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2024
Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique.
Int. J. Circuit Theory Appl., May, 2024

2023
Unleashing the Power of Differential Fault Attacks on QARMAv2.
IACR Cryptol. ePrint Arch., 2023

2022
Risk Analysis of Green Supply Chain Using a Hybrid Multi-Criteria Decision Model: Evidence from Laptop Manufacturer Industry.
Axioms, 2022

2020
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2016
An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016


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