Santanu Chattopadhyay

Orcid: 0000-0002-1227-0732

According to our database1, Santanu Chattopadhyay authored at least 162 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

2023
Application Mapping Onto Manycore Processor Architectures Using Active Search Framework.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

2022
A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits.
IEEE Trans. Emerg. Top. Comput., 2022

Conformance Testing for Finite State Machines Guided by Deep Neural Network.
J. Circuits Syst. Comput., 2022

Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021
LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design.
Microprocess. Microsystems, November, 2021

Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption.
IEEE Trans. Emerg. Top. Comput., 2021

Embedding delay-based physical unclonable functions in networks-on-chip.
IET Circuits Devices Syst., 2021

A Deep Neural Network Guided Testing Approach for Finite State Machines.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

2020
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design.
Microprocess. Microsystems, 2020

Thermal-aware detour routing in 3D NoCs.
J. Parallel Distributed Comput., 2020

A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection.
Integr., 2020

Hardware IP Protection Using Logic Encryption and Watermarking.
Proceedings of the IEEE International Test Conference, 2020

On Securing Scan Obfuscation Strategies Against ScanSAT Attack.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Thermal-aware task allocation and scheduling for periodic real-time applications in mesh-based heterogeneous NoCs.
Real Time Syst., 2019

Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems.
ACM J. Emerg. Technol. Comput. Syst., 2019

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip.
CoRR, 2019

A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis.
Proceedings of the TENCON 2019, 2019

Enhanced Schedulability via Minimal Routing with Mapping and Priority Assignment for Real-Time Network-on-chip.
Proceedings of the TENCON 2019, 2019

Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach.
Proceedings of the 2019 International Conference on Information Technology (ICIT), 2019

2018
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design.
IEEE Trans. Computers, 2018

Task mapping and scheduling for network-on-chip based multi-core platform with transient faults.
J. Syst. Archit., 2018

Design and evaluation of ZMesh topology for on-chip interconnection networks.
J. Parallel Distributed Comput., 2018

Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution.
Integr., 2018

Reliability-aware application mapping onto mesh based Network-on-Chip.
Integr., 2018

Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits.
CoRR, 2018

Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Thermal Aware Application Mapping and Frequency Scaling for Mesh-Based Network-On-Chip Design.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

On Finding Suitable Key-Gate Locations In Logic Encryption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform.
ACM Trans. Embed. Comput. Syst., 2017

Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform.
J. Syst. Archit., 2017

Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture.
J. Circuits Syst. Comput., 2017

Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design.
Integr., 2017

Temperature and data size trade-off in dictionary based test data compression.
Integr., 2017

A New Logic Encryption Strategy Ensuring Key Interdependency.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Enhancing security of logic encryption using embedded key generation unit.
Proceedings of the International Test Conference in Asia, 2017

Runtime mitigation of illegal packet request attacks in Networks-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design.
ACM Trans. Embed. Comput. Syst., 2016

Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels.
ACM Trans. Archit. Code Optim., 2016

Small Test Set Generation with High Diagnosability.
J. Circuits Syst. Comput., 2016

Optimization of the IEEE 1687 access network for hybrid access schedules.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Thermal-Safe Schedule Generation for System-on-Chip Testing.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A strategy for fault tolerant reconfigurable Network-on-Chip design.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design.
Proceedings of the 2016 3rd International Conference on Recent Advances in Information Technology (RAIT), 2016

A reliability aware application mapping onto mesh based Network-on-Chip.
Proceedings of the 2016 3rd International Conference on Recent Advances in Information Technology (RAIT), 2016

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip.
Microprocess. Microsystems, 2015

Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores.
J. Syst. Archit., 2015

Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes.
J. Syst. Archit., 2015

A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip.
J. Circuits Syst. Comput., 2015

Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling.
Integr., 2015

Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation.
Int. J. High Perform. Syst. Archit., 2015

Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Thermal-Aware Test Data Compression Using Dictionary Based Coding.
Proceedings of the 28th International Conference on VLSI Design, 2015

Particle swarm optimization approach for low temperature BIST.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A constructive heuristic for application mapping onto an express channel based Network-on-Chip.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Power- and thermal-aware testing of VLSI circuits and systems.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

GA based diagnostic test pattern generation for transition faults.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Test set customization for improved fault diagnosis without sacrificing coverage.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A hardware based low temperature solution for VLSI testing using decompressor side masking.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fault tolerant mesh based Network-on-Chip architecture.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2014

Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip.
J. Syst. Archit., 2014

Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

A locally reconfigurable Network-on-Chip architecture and application mapping onto it.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

A spare link based reliable Network-on-Chip design.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

A spare router based reliable Network-on-Chip design.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A survey on application mapping strategies for Network-on-Chip design.
J. Syst. Archit., 2013

Application-Specific Network-on-Chip synthesis with flexible router Placement.
J. Syst. Archit., 2013

Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Aggresive scan chain masking for improved diagnosis of multiple scan chain failures.
Proceedings of the 18th IEEE European Test Symposium, 2013

An ATE assisted DFD technique for volume diagnosis of scan chains.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during Testing.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router.
Microprocess. Microsystems, 2012

Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off.
J. Circuits Syst. Comput., 2012

Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing.
Integr., 2012

Efficient don't care filling and scan chain masking for low-power testing.
Int. J. Comput. Aided Eng. Technol., 2012

Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique.
IET Comput. Digit. Tech., 2012

A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection.
Proceedings of the 25th International Conference on VLSI Design, 2012

An Efficient Technique for Longest Prefix Matching in Network Routers.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization.
Proceedings of the International Symposium on Electronic System Design, 2012

Confidence Based Power Aware Testing.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
And-or-XOR Network Synthesis with Area-Power Trade-Off.
J. Circuits Syst. Comput., 2011

Low power finite state machine synthesis using power-gating.
Integr., 2011

Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
Customizing pattern set for test power reduction via improved X-identification and reordering.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis.
J. Low Power Electron., 2009

Genetic algorithm-based FSM synthesis with area-power trade-offs.
Integr., 2009

Synthesis & Testing for Low Power.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic.
Proceedings of the ARTCom 2009, 2009

Efficient Don't Care Filling for Power Reduction during Testing.
Proceedings of the ARTCom 2009, 2009

Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing.
Proceedings of the ARTCom 2009, 2009

2008
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology.
Int. J. High Perform. Syst. Archit., 2008

Integrated Power-Gating and State Assignment for Low Power FSM Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

An efficient finite precision realization of the block adaptive decision feedback equalizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Don't care filling for power minimization in VLSI circuit testing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An efficient greedy approach to PLA folding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

AND-XOR Network Synthesis with Area-Power Trade-off.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Mesh-of-Tree Based Scalable Network-on-Chip Architecture.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

A Novel Technique to Reduce both Leakage and Peak Power during Scan Testing.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

Mesh-of-tree deterministic routing for network-on-chip architecture.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Three-level AND-OR-XOR network synthesis: A GA based approach.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach.
Proceedings of the Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence, 2007

Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Test Data Compression by Spilt-VIHC (SVIHC).
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Synthesis of Finite State Machines for Low Power and Testability.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach.
Comput. J., 2005

A Combinational Logic Mapper for Actel's SX/AX Family.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Flip-flop chaining architecture for power-efficient scan during test application.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Model checking on state transition diagram.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach".
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator.
IEEE Trans. Computers, 2001

Theory and application of non-group cellular automata for message authentication.
J. Syst. Archit., 2001

A Novel Strategy to Test Core Based Designs.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

An ASIC for Cellular Automata Based Message Authentication.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1998
Cellular-Automata-Array-Based Diagnosis of Board Level Faults.
IEEE Trans. Computers, 1998

Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Parallel Decoder for Cellular Automata Based Byte Error Correcting Code.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
CAA Decoder for Cellular Automata Based Byte Error Correcting Code.
IEEE Trans. Computers, 1996

Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.
IEEE Trans. Computers, 1996

Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Cellular automata based architecture of a database query processor.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Board level fault diagnosis using cellular automata array.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994
A new look into the acquisition properties of a second-order digital phase locked loop.
IEEE Trans. Commun., 1994

1990
Symmetric lock-range multilevel quantized digital phase locked FM demodulator.
IEEE Trans. Commun., 1990


  Loading...