Sanmitra Banerjee

Orcid: 0000-0002-1136-9220

According to our database1, Sanmitra Banerjee authored at least 34 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024

DOCTOR: Dynamic On-Chip Remediation Against Temporally-Drifting Thermal Variations Toward Self-Corrected Photonic Tensor Accelerators.
CoRR, 2024

2023
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

On the Impact of Uncertainties in Silicon-Photonic Neural Networks.
IEEE Des. Test, April, 2023

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., March, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.
CoRR, 2023

Compact and Low-Loss PCM-based Silicon Photonic MZIs for Photonic Neural Networks.
CoRR, 2023

Analysis of Optical Loss and Crosstalk Noise in MZI-based Coherent Photonic Neural Networks.
CoRR, 2023

Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs <sup>*</sup>.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs.
Proceedings of the IEEE International Test Conference, 2023

2022
Design Automation and Test Solutions for Monolithic 3D ICs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Characterizing Coherent Integrated Photonic Neural Networks under Imperfections.
CoRR, 2022

Characterization and Optimization of Integrated Silicon-Photonic Neural Networks under Fabrication-Process Variations.
CoRR, 2022

CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration.
Proceedings of the IEEE International Test Conference, 2022

Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Structural Test Generation for AI Accelerators using Neural Twins.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Observation Point Insertion Using Deep Learning.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Optimizing Coherent Integrated Photonic Neural Networks under Random Uncertainties.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Modeling Silicon-Photonic Neural Networks under Uncertainties.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Advances in Design and Test of Monolithic 3-D ICs.
IEEE Des. Test, 2020

RTL-to-GDS Design Tools for Monolithic 3D ICs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs<sup>∗</sup>.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.
Proceedings of the 24th IEEE European Test Symposium, 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Detection of Third Heart Sound Using Variational Mode Decomposition.
IEEE Trans. Instrum. Meas., 2018

Grading heart sounds through variational mode decomposition and higher order spectral features.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2018


  Loading...