Sanjukta Bhanja

CoRR, 2021

PIRM: Processing In Racetrack Memories.

[BibT_eX]

[DOI]

CoRR, 2021

2020

MatlabHTM: A sequence memory model of neocortical layers for anomaly detection.

[BibT_eX]

[DOI]

Ilia A. Bautista Adames

Sudeep Sarkar

SoftwareX, 2020

2019

The Power of Orthogonality.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

2018

Non-Boolean Computing with Spintronic Devices.

[BibT_eX]

[DOI]

Kawsher A. Roxy

Found. Trends Electron. Des. Autom., 2018

2017

Variability tolerant reading of nanomagnetic energy minimizing co-processor.

[BibT_eX]

[DOI]

Kawsher A. Roxy

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Integrating emerging memory technologies into undergraduate logic design course: The impact of context based teaching.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

2016

MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells.

[BibT_eX]

[DOI]

Kevin Scott

ACM J. Emerg. Technol. Comput. Syst., 2016

Survey of Emerging Technology Based Physical Unclonable Funtions.

[BibT_eX]

[DOI]

Ilia A. Bautista Adames

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies.

[BibT_eX]

[DOI]

Aida Todri-Sanial

ACM J. Emerg. Technol. Comput. Syst., 2015

2014

STT-Based Non-Volatile Logic-in-Memory Framework.

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Nano Magnetic STT-Logic Partitioning for Optimum Performance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

2012

Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Evaluation of circuit styles and VLSI logic designs of pentacene OTFTs.

[BibT_eX]

[DOI]

Sneta Mishra

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Non-destructive variability tolerant differential read for non-volatile logic.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011

Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays.

[BibT_eX]

[DOI]

Anita Kumari

IEEE Trans. Very Large Scale Integr. Syst., 2011

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Novel knowledge module on fusion of logic and memory to undergraduate students.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

QCAPro - An error-power estimation tool for QCA circuit design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A review of magnetic cellular automata systems.

[BibT_eX]

[DOI]

Javier F. Pulecio

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009

Probabilistic Error Modeling for Nano-Domain Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis

[BibT_eX]

[DOI]

CoRR, 2009

An Error Model to Study the Behavior of Transient Errors in Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

CNT logic knowledge module integrated in digital CMOS logic design course.

[BibT_eX]

[DOI]

Anita Kumari

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Defect characterization in magnetic field coupled arrays.

[BibT_eX]

[DOI]

Anita Kumari

Javier F. Pulecio

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits.

[BibT_eX]

[DOI]

Sudeep Sarkar

IEEE Trans. Very Large Scale Integr. Syst., 2008

Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course.

[BibT_eX]

[DOI]

Saket Srivastava

IEEE Trans. Educ., 2008

2007

Hierarchical Probabilistic Macromodeling for QCA Circuits.

[BibT_eX]

[DOI]

Saket Srivastava

IEEE Trans. Computers, 2007

QCA Circuits for Robust Coplanar Crossing.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Integrating Nano-logic into an Undergraduate Logic Design Course.

[BibT_eX]

[DOI]

Saket Srivastava

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Probabilistic maximum error modeling for unreliable logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Wide Limited Switch Dynamic Logic Circuit Implementations.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Novel designs for thermally robust coplanar crossing in QCA.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

An Accurate Probalistic Model for Error Detection.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Causal probabilistic input dependency learning for switching model in VLSI circuits.

[BibT_eX]

[DOI]

Nirmal Ramalingam

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Any-time probabilistic switching model using bayesian networks.

[BibT_eX]

[DOI]

Shiva Shankar Ramani

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

Switching activity estimation of VLSI circuits using Bayesian networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

2002

Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

1998

A Qualitative Expert System for Clinical Trial Assignment.

[BibT_eX]

[DOI]