Sanjoy Kumar Dey

According to our database, Sanjoy Kumar Dey authored at least 8 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits.

Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi, Gaurav Agrawal, Krishna Thakur, Deependra Kumar Jain, Alvin Leng Sun Loke, Atul Kumar, Manish Kumar Upadhyay, Bhawna, Sanjoy Kumar Dey

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

A low-power resistive tail dynamic comparator with self-shut mechanism.

Sanjoy Kumar Dey, Mukul Sarkar, Shouribrata Chatterjee

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Energy efficiency optimization in Strong-Arm latch-based dynamic comparator by capacitor distribution.

Sanjoy Kumar Dey, Mukul Sarkar, Shouribrata Chatterjee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Large Network of Wide- Range Analog Voltage Observers for Debug & Testability.

Tapas Nandy, Ashish Joshi, Sanjoy Kumar Dey

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

Modelling the Effect of Output-Dependent Integrator Gain on the Unadjusted Error of Inverter Based 1^stOrder $\Sigma\Delta$ ADC.

Ashish Joshi, Tapas Nandy, Aashish T. R, Mayank Devam, Sanjoy Kumar Dey

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2008

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.

Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2006

An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC.

Sanjoy Kumar Dey, Swapna Banerjee

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC.

Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005