Sanjeev Mehta

According to our database, Sanjeev Mehta authored at least 6 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC.

Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Large Dynamic Range Readout Integrated Circuit for Infrared Detectors.

Hari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini, Arup Roy Chowdhury, A. S. Kiran Kumar, Dinesh Kumar Sharma

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2015

An all digital delay lock loop architecture for high precision timing generator.

Mohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Bipolar voltage level shifter.

Hari Shanker Gupta, Shweta Kirkire, Sunil Bhati, Ravi Shankar Chaurasia, Sanjeev Mehta, Arup Roy Choudhary, Dipen Patel, Jaymin Vaghela

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

Implementation of high performance Readout Integrated Circuit.

Hari Shanker Gupta, Subhananda Chakrabarti, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. S. Kiran Kumar, Sanjeev Mehta, Sandip Paul, Ravi Shankar Chaurasia, Arup Roy Chowdhury

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Generic and programmable Timing Generator for CCD detectors.

Parth Shah, Bhavesh Soni, Mohammad Waris, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury

Proceedings of the 2014 International Conference on Advances in Computing, 2014