Sanjaya M. V

According to our database, Sanjaya M. V authored at least 2 papers between 2020 and 2022.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2022

An hardware accelerator design of Mobile-Net model on FPGA.

Sanjaya M. V, Madhav Rao

Proceedings of the Second International Conference on AI-ML Systems, 2022

2020

Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM).

Karthik S, Karthick D, Sanjaya M. V, Madhav Rao

Proceedings of the International SoC Design Conference, 2020