Sanjay Parihar
Orcid: 0009-0001-8003-6956
According to our database1,
Sanjay Parihar
authored at least 8 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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2024
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Bibliography
2024
An In-Memory-Computing Binary Neural Network Architecture With In-Memory Batch Normalization.
IEEE Access, 2024
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
An Energy-Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network.
IEEE Access, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2016
Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014