Sanjay Kumar Jana

Orcid: 0000-0001-5143-8000

According to our database1, Sanjay Kumar Jana authored at least 9 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2023
Design of a Power-Performance-Area (PPA) Optimized MOS Current Mode Logic Pre-scaler.
Circuits Syst. Signal Process., October, 2023

Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL.
J. Circuits Syst. Comput., February, 2023

2022
Design of a 1.29-1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation.
J. Circuits Syst. Comput., 2022

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz- 4.2 GHz for Phase-Locked Loop Application.
Circuits Syst. Signal Process., 2022

2021
Design of High Gain Folded Cascode OTA-Based Transconductance-Capacitance Loop Filter for PLL Applications.
J. Circuits Syst. Comput., 2021

Power and area-efficient static current mode logic frequency divider in 180-nm complementary metal-oxide-semiconductor technology.
Int. J. Circuit Theory Appl., 2021

2020
Design of Pass Transistor based Phase Frequency Detector for Fast Frequency Acquisition Phase Locked Loop.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

Comparison and Performance Analysis of Ring Oscillators and Current-Starved VCO in 180-nm CMOS Technology.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2018
Improving Children's Speech Recognition Through Time Scale Modification Based Speaking Rate Adaptation.
Proceedings of the 2018 International Conference on Signal Processing and Communications (SPCOM), 2018


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