Sangyeun Cho

Sanghoan Chang

Insoon Jo

Proceedings of the 31st IEEE International Conference on Data Engineering, 2015

Recent advances in flash solutions.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Data Engineering Workshops, 2015

F2FS: A New File System for Flash Storage.

[BibT_eX]

[DOI]

Proceedings of the 13th USENIX Conference on File and Storage Technologies, 2015

Fast memory and storage architectures for the big data era.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

COMeT+: Continuous Online Memory Testing with Multi-Threading Extension.

[BibT_eX]

[DOI]

Musfiq Rahman

IEEE Trans. Computers, 2014

Refresh Now and Then.

[BibT_eX]

[DOI]

Seungjae Baek

IEEE Trans. Computers, 2014

Keynote: "Flashing the roads ahead".

[BibT_eX]

[DOI]

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Design space exploration of an NVM-based memory hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Stash directory: A scalable directory for many-core coherence.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

The Multi-streamed Solid-State Drive.

[BibT_eX]

[DOI]

Proceedings of the 6th USENIX Workshop on Hot Topics in Storage and File Systems, 2014

2013

Accurately modeling superscalar processor performance with reduced trace.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2013

Data Dependent Sparing to Manage Better-Than-Bad Blocks.

[BibT_eX]

[DOI]

Rakan Maddah

IEEE Comput. Archit. Lett., 2013

Power of One Bit: Increasing Error Correction Capability with Data Inversion.

[BibT_eX]

[DOI]

Rakan Maddah

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Memorage: emerging persistent RAM based malleable main memory and storage architecture.

[BibT_eX]

[DOI]

Ju-Young Jung

Proceedings of the International Conference on Supercomputing, 2013

Active disk meets flash: a case for intelligent SSDs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2013

2012

Predicting Coherence Communication by Tracking Synchronization Points at Run Time.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Characterizing Machines and Workloads on a Google Cluster.

[BibT_eX]

[DOI]

Zitao Liu

Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

A Theoretical Design for SSD Texture Storage.

[BibT_eX]

[DOI]

Andrew Conn

Joseph V. Cavanaugh

Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory.

[BibT_eX]

[DOI]

Rakan Maddah

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

2011

Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

DEFCAM: A design and evaluation framework for defect-tolerant cache memories.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2011

Advanced hashing schemes for packet forwarding using set associative memory architectures.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

C-AMTE: A location mechanism for flexible cache management in chip multiprocessors.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

Fast, Energy Efficient Scan inside Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011

COMeT: Continuous Online Memory Test.

[BibT_eX]

[DOI]

Musfiq Rahman

Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011

A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined Tries.

[BibT_eX]

[DOI]

Michel Hanna

Proceedings of the NETWORKING 2011, 2011

An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing.

[BibT_eX]

[DOI]

Taecheol Oh

Proceedings of the MASCOTS 2011, 2011

Scalable Multi-cache Simulation Using GPUs.

[BibT_eX]

[DOI]

Michael Moeng

Proceedings of the MASCOTS 2011, 2011

In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces.

[BibT_eX]

[DOI]

Proceedings of the MASCOTS 2011, 2011

PRISM: Zooming in persistent RAM storage behavior.

[BibT_eX]

[DOI]

Ju-Young Jung

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

CloudCache: Expanding and shrinking private caches.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2011

Dynamic co-management of persistent RAM main memory and storage resources.

[BibT_eX]

[DOI]

Ju-Young Jung

Proceedings of the 8th Conference on Computing Frontiers, 2011

BarrierWatch: characterizing multithreaded workloads across and within program-defined epochs.

[BibT_eX]

[DOI]

Proceedings of the 8th Conference on Computing Frontiers, 2011

MAESTRO: Orchestrating predictive resource management in future multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

On the Interplay of Parallelization, Program Performance, and Energy Consumption.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2010

PERFECTORY: A Fault-Tolerant Directory Memory Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2010

A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2010

StealthWorks: Emulating Memory Errors.

[BibT_eX]

[DOI]

Musfiq Rahman

Proceedings of the Runtime Verification - First International Conference, 2010

A content-aware block placement algorithm for reducing PRAM storage bit writes.

[BibT_eX]

[DOI]

Brian Wongchaowart

Marian Kamal Iskander

Proceedings of the IEEE 26th Symposium on Mass Storage Systems and Technologies, 2010

StimulusCache: Boosting performance of chip multiprocessors with excess cache.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

An intra-tile cache set balancing scheme.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

Augmented FIFO Cache Replacement Policies for Low-Power Embedded Processors.

[BibT_eX]

[DOI]

Lory Al Moakar

J. Circuits Syst. Comput., 2009

CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP Lookup.

[BibT_eX]

[DOI]

Proceedings of the NETWORKING 2009, 2009

Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Accurately approximating superscalar processor performance from traces.

[BibT_eX]

[DOI]

Shayne Evans

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

Dynamic cache clustering for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 23rd international conference on Supercomputing, 2009

ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Progressive hashing for packet processing using set associative memory.

[BibT_eX]

[DOI]

Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the PACT 2009, 2009

2008

Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems.

[BibT_eX]

[DOI]

Tao Li

Onur Mutlu

IEEE Micro, 2008

Corollaries to Amdahl's Law for Energy.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2008

Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

Early prediction of product performance and yield via technology benchmark.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Preliminary studies to develop a ubiquitous computing and health-monitoring system for wheelchair users.

[BibT_eX]

[DOI]

Jongbae Kim

Seung-Jae Kim

Proceedings of the 3rd International ICST Conference on Body Area Networks, 2008

2007

Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Performance of Graceful Degradation for Cache Faults.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology.

[BibT_eX]

[DOI]

Choongyeun Cho

Daeik D. Kim

Jonghae Kim

Jean-Olivier Plouchart

Daihyun Lim

Robert Trzcinski

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Exploring the interplay of yield, area, and performance in processor caches.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

I-cache multi-banking and vertical interleaving.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Reducing cache traffic and energy with macro data load.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A flexible data to L2 cache mapping approach for future multicore processors.

[BibT_eX]

[DOI]

Proceedings of the 2006 workshop on Memory System Performance and Correctness, 2006

2001

A High-Bandwidth Memory Pipeline for Wide Issue Processors.

[BibT_eX]

[DOI]

Pen-Chung Yew

IEEE Trans. Computers, 2001

A Low-Power Cache Design for CalmRISC<sup>TM</sup>-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999

Design of a bus-based shared-memory multiprocessor DICE.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1999

Coherence and Replacement Protocol of DICE-A Bus-Based COMA Multiprocessor.

[BibT_eX]

[DOI]

Jinseok Kong

J. Parallel Distributed Comput., 1999

Access Region Locality for High-Bandwidth Processor Memory System Design.

[BibT_eX]

[DOI]

Pen-Chung Yew

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor.

[BibT_eX]

[DOI]

Pen-Chung Yew

Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

1998

On timing constraints of snooping in a bus-based COMA multiprocessor.

[BibT_eX]

[DOI]

Jinseok Kong

Microprocess. Microsystems, 1998

High-Level Information - An Approach for Integrating Front-End and Back-End Compilers.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1996

Global Bus Design of a Bus-Based COMA Multiprocessor DICE.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Reducing Coherence Overhead in Shared-Bus Multiprocessors.

[BibT_eX]

[DOI]