Sangwan Lee

According to our database, Sangwan Lee authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 102-Gb/s/lane 1.4-V_ppd Linear Range PAM-8 Receiver Frontend With Multi-Path Continuous-Time Linear Equalization in 28-nm CMOS.

Sangwan Lee, Hyeongmin Seo, Seungwoo Son, Sunoh Yeom, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, November, 2024

A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology.

Youngmin Oh, Hyunwoo Im, Jeonghyu Yang, Eunji Song, Dongjun Lee, Sangwan Lee, Tae-ho Shin, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS.

Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023

A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm.

Jeonghyu Yang, Eunji Song, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Tae-ho Shin, Jaeduk Han

Proceedings of the IEEE International Solid- State Circuits Conference, 2023