Sangjoon Hwang
According to our database1,
Sangjoon Hwang
authored at least 12 papers
between 2017 and 2024.
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Bibliography
2024
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5<sup>th</sup>-Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
IEEE J. Solid State Circuits, 2023
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ.
IEEE J. Solid State Circuits, 2023
2022
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017