Sangjin Byun

Orcid: 0000-0003-4633-7648

According to our database1, Sangjin Byun authored at least 20 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
An 884MHz, -41.8dBm Input Power Sensitivity, 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2020
A Poly Resistor Based Time Domain CMOS Temperature Sensor with 9b SAR and Fine Delay Line.
Sensors, 2020

Categorization and Characterization of Time Domain CMOS Temperature Sensors.
Sensors, 2020

2017
On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling.
IET Circuits Devices Syst., 2016

1∼3 GHz VCO with rail-to-rail V<sub>CONT</sub> range.
IEICE Electron. Express, 2016

2014
Analysis and Design of CMOS Received Signal Strength Indicator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.
IET Circuits Devices Syst., 2013

2012
Simple odd number frequency divider with 50% duty cycle.
IEICE Electron. Express, 2012

2011
A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications.
IEICE Electron. Express, 2011

2010
Charge Pump circuit with wide range digital leakage current mismatch compensator.
IEICE Electron. Express, 2010

2008
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology.
IEEE J. Solid State Circuits, 2008

2006
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.
IEEE J. Solid State Circuits, 2006

A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer.
IEEE J. Solid State Circuits, 2005

2003
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator.
IEEE J. Solid State Circuits, 2003

1999
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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