Sanghune Park

According to our database, Sanghune Park authored at least 10 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.

Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin

IEEE J. Solid State Circuits, January, 2024

2023

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques.

Kihwan Seong, Donguk Park, Gyeom-Je Bae, Hyunwoo Lee, Youngseob Suh, Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.

Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL.

Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2020

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.

Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim, Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyounghoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.

Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX.

Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghune Park, Chulwoo Kim

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.

Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park

Proceedings of the International SoC Design Conference, 2018

2017

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller.

Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology.

Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016