Sang-uhn Cha
According to our database1,
Sang-uhn Cha
authored at least 5 papers
between 2007 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
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2020
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2013
IEICE Electron. Express, 2013
2007
High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007