Sang Phill Park
Orcid: 0000-0002-2951-8474
According to our database1,
Sang Phill Park
authored at least 21 papers
between 2007 and 2016.
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Bibliography
2016
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.
IEEE J. Solid State Circuits, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009
IEEE Des. Test Comput., 2009
2008
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007