Sang H. Dhong

According to our database, Sang H. Dhong authored at least 32 papers between 1988 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2015

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology.

Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

A 4-GHz universal high-frequency on-chip testing platform for IP validation.

Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.

Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.

Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm² per MB.

Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Prospective for nanowire transistors.

Jean-Pierre Colinge, Sang H. Dhong

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2008

Challenges at 45nm and beyond.

Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata

IBM J. Res. Dev., 2007

Cell Broadband Engine Processor Design Methodology.

Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Implementation of the 65nm Cell Broadband Engine.

Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor.

James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen

IEEE J. Solid State Circuits, 2006

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.

Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong

IEEE J. Solid State Circuits, 2006

The microarchitecture of the synergistic processor for a cell processor.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata

IEEE J. Solid State Circuits, 2006

A cycle accurate power estimation tool.

Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Power-Conscious Design of the Cell Processor's Synergistic Processor Element.

Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman

IEEE Micro, 2005

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.

Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara

IEEE Micro, 2005

The circuit design of the synergistic processor element of a CELL processor.

Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.

Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2000

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.

Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki

IEEE J. Solid State Circuits, 2000

Custom circuit design as a driver of microprocessor performance.

David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel

IBM J. Res. Dev., 2000

"Timing closure by design, " a high frequency microprocessor design methodology.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia

Proceedings of the 37th Conference on Design Automation, 2000

1999

A 1-GHz logic circuit family with sense amplifiers.

Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong

IEEE J. Solid State Circuits, 1999

1998

Designing for a gigahertz [guTS integer processor].

H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi

IEEE Micro, 1998

A 1.0-GHz single-issue 64-bit powerPC integer processor.

Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric

IEEE J. Solid State Circuits, 1998

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.

David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A 690 ps read-access latency register file for a GHz integer microprocessor.

Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Design methodology for a 1.0 GHz microprocessor.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1995

A variable precharge voltage sensing.

Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira

IEEE J. Solid State Circuits, January, 1995

A 64Kb - 32 DRAM for graphics applications.

Toshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura

IBM J. Res. Dev., 1995

A low-noise TTL-compatible CMOS off-chip driver circuit.

Sang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata

IBM J. Res. Dev., 1995

1989

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.

Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano

IEEE J. Solid State Circuits, October, 1989

1988

High-speed sensing scheme for CMOS DRAMs.

Sang H. Dhong, Nicky Chau-Chun Lu, Wei Hwang, Stephen A. Parke

IEEE J. Solid State Circuits, February, 1988