Sang-Bo Lee

According to our database1, Sang-Bo Lee authored at least 6 papers between 1996 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
0
1
2
3
1
1
2
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control.
IEEE J. Solid State Circuits, 2005

2000
A low-jitter mixed-mode DLL for high-speed DRAM applications.
IEEE J. Solid State Circuits, 2000

1998
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme.
IEEE J. Solid State Circuits, 1998

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system.
IEEE J. Solid State Circuits, 1998

1997
Low-voltage, high-speed circuit designs for gigabit DRAMs.
IEEE J. Solid State Circuits, 1997

1996
A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth.
IEEE J. Solid State Circuits, 1996


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