Sandip Tiwari

According to our database, Sandip Tiwari authored at least 15 papers between 2004 and 2017.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2017

On the Physical Underpinnings of the Unusual Effectiveness of Probabilistic and Neural Computation.

Sandip Tiwari, Damien Querlioz

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2015

Implications of Scales in Processing of Information.

Sandip Tiwari

Proc. IEEE, 2015

2014

Inexact computing using probabilistic circuits: Ultra low-power digital processing.

Jaeyoon Kim, Sandip Tiwari

ACM J. Emerg. Technol. Comput. Syst., 2014

2012

Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS.

Jaeyoon Kim, Paul Michael Solomon, Sandip Tiwari

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Nanostructure devices for logic and memory and beyond.

Sandip Tiwari

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011

A Single Element Phase Change Memory.

Sang-Hyeon Lee, Moonkyung Mark Kim, Byung-ki Cheong, Jooyeon Kim, Jo-Won Lee, Sandip Tiwari

IEICE Trans. Electron., 2011

Inexact computing for ultra low-power nanometer digital circuit design.

Jaeyoon Kim, Sandip Tiwari

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

2007

Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor.

Sandip Tiwari

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space.

Christianto C. Liu, Sandip Tiwari

IEEE Trans. Circuits Syst. II Express Briefs, 2006

2005

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception.

Uygar Avci, Sandip Tiwari

Microelectron. J., 2005

Bridging the Processor-Memory Performance Gapwith 3D IC Technology.

Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari

IEEE Des. Test Comput., 2005

Mapping system-on-chip designs from 2-D to 3-D ICs.

Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Defect tolerance for nanocomputer architecture.

Arvind Kumar, Sandip Tiwari

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

A power-performance adaptive low voltage analog circuit design using independently controlled double gate CMOS technology.

Arvind Kumar, Sandip Tiwari

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics.

Arvind Kumar, Sandip Tiwari

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004