Sandip Ray

Orcid: 0000-0002-8671-5052

Affiliations:
  • University of Florida, Gainesville, FL, USA
  • University of Texas at Austin, USA (former)


According to our database1, Sandip Ray authored at least 130 papers between 2004 and 2024.

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Timeline

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Bibliography

2024
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

ReCAP: Protecting Cooperative Adaptive Cruise Control Against Multi-Channel Perception Adversary.
IEEE Trans. Intell. Transp. Syst., November, 2024

System-on-Chip Information Flow Validation Under Asynchronous Resets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

ViSE: Digital Twin Exploration for Automotive Functional Safety and Cybersecurity.
J. Hardw. Syst. Secur., June, 2024

Guarding Deep Learning Systems With Boosted Evasion Attack Detection and Model Update.
IEEE Internet Things J., March, 2024

Correct-by-Construction Design of Custom Accelerator Microarchitectures.
IEEE Trans. Computers, January, 2024

Digital Twins for IoT-Driven Energy Systems: A Survey.
IEEE Access, 2024

Nuclear Quadrupole Resonance for Substance Detection.
IEEE Access, 2024

PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

DRIFT: Resilient Distributed Coordinated Fleet Management Against Communication Attacks.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2024

DT-IoMT: A Digital Twin Reference Model for Secure Internet of Medical Things.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Adaptive Robotic Arm System for Wheelchair Assistance in Autonomous Vehicles.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

PhD Project: Reconfigurable Network on Chip Architecture Through Topology Obfuscation For Protecting SoC Against Reverse Engineering.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2023
ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks.
ACM Trans. Embed. Comput. Syst., October, 2023

A Virtual Prototyping Platform for Exploration of Vehicular Electronics.
IEEE Internet Things J., September, 2023

TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs.
IEEE Trans. Computers, August, 2023

AroMa: Evaluating Deep Learning Systems for Stealthy Integrity Attacks on Multi-tenant Accelerators.
ACM J. Emerg. Technol. Comput. Syst., April, 2023

SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

AINNS: All-Inclusive Neural Network Scheduling Via Accelerator Formalization.
IEEE Trans. Computers, February, 2023

Virtual Prototyping for Modern Internet-of-Things Applications: A Survey.
IEEE Access, 2023

VeCAEP: A Hands-on Exploration Platform for Vehicular Communication Attacks.
Proceedings of the 97th IEEE Vehicular Technology Conference, 2023

Poster: Vehicle-to-Infrastructure Security for Reduced Speed Work Zone.
Proceedings of the Twenty-fourth International Symposium on Theory, 2023

Poster: Scenario Creation for Immersive Automotive Security Exploration.
Proceedings of the Twenty-fourth International Symposium on Theory, 2023

Poster: Efficient Exploration of Automotive Ranging Sensor Attacks.
Proceedings of the Twenty-fourth International Symposium on Theory, 2023

GERALT: Real-time Detection of Evasion Attacks in Deep Learning Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

sc IVE: An Immersive Virtual Environment for Automotive Security Exploration.
Proceedings of the Immersive Learning Research Network - 9th International Conference, 2023

Continuous Monitoring for Diagnosis: A Wearable for Covid-19 Detection in Symptomatic Patients.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

Exploration of Machine Learning Attacks in Automotive Systems Using Physical and Mixed Reality Platforms.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023

Work-in-Progress: Towards Evaluating CNNs Against Integrity Attacks on Multi-tenant Computation.
Proceedings of the International Conference on Compilers, 2023

2022
SoCCom: Automated Synthesis of System-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Resilient Cooperative Adaptive Cruise Control for Autonomous Vehicles Using Machine Learning.
IEEE Trans. Intell. Transp. Syst., 2022

GCONV Chain: Optimizing the Whole-Life Cost in End-to-end CNN Acceleration.
IEEE Trans. Computers, 2022

Dandelion: Boosting DNN Usability Under Dataset Scarcity.
IEEE Trans. Computers, 2022

HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption.
IEEE Embed. Syst. Lett., 2022

Security of Multi-Agent Cyber-Physical Systems: A Survey.
IEEE Access, 2022

Deep-Learning-Based Anomaly Detection for Lane-Changing Decisions.
Proceedings of the 2022 IEEE Intelligent Vehicles Symposium, 2022

CAVELIER: Automated Security Evaluation for Connected Autonomous Vehicle Applications.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2022

Autohal: An Exploration Platform for Ranging Sensor Attacks on Automotive Systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022

Resiliency in Connected Vehicle Applications: Challenges and Approaches for Security Validation.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

FirVer: Concolic Testing for Systematic Validation of Firmware Binaries.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets.
IACR Cryptol. ePrint Arch., 2021

Optimizing the Whole-life Cost in End-to-end CNN Acceleration.
CoRR, 2021

Deep-Learning-Based Intrusion Detection for Autonomous Vehicle-Following Systems.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

VIVE: Virtualization of Vehicular Electronics for System-level Exploration.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

Replace: Real-time Security Assurance in Vehicular Platoons Against V2V Attacks.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

Do VIR: Virtualizing Food Donation Distribution through Mobile Application and Cloud-Based Supply Chain Management.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

Universal Neural Network Acceleration via Real-Time Loop Blocking.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction.
Proceedings of the 26th IEEE European Test Symposium, 2021

CASTLE: Architecting Assured System-on-Chip Firmware Integrity.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

SSEL: An Extensible Specification Language for SoC Security.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
Resilient System-on-Chip Designs With NoC Fabrics.
IEEE Trans. Inf. Forensics Secur., 2020

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.
CoRR, 2020

2019
Guest Editors' Introduction: Secure Automotive Systems.
IEEE Des. Test, 2019

Security of Emergent Automotive Systems: A Tutorial Introduction and Perspectives on Practice.
IEEE Des. Test, 2019

Post-Quantum Lattice-Based Cryptography Implementations: A Survey.
ACM Comput. Surv., 2019

A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

REDEM: Real-Time Detection and Mitigation of Communication Attacks in Connected Autonomous Vehicle Applications.
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019

Safety, Security, and Reliability: The Automotive Robustness Problem and an Architectural Solution.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

An Adaptable System-on-Chip Security Architecture for Internet of Things Applications.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
System-on-Chip Platform Security Assurance: Architecture and Validation.
Proc. IEEE, 2018

Internet-of-Things Security and Vulnerabilities: Taxonomy, Challenges, and Practice.
J. Hardw. Syst. Secur., 2018

ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Protecting the supply chain for automotives and IoTs.
Proceedings of the 55th Annual Design Automation Conference, 2018

Application level hardware tracing for scaling post-silicon debug.
Proceedings of the 55th Annual Design Automation Conference, 2018

System-on-chip security architecture and CAD framework for hardware patch.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Postsilicon Trace Signal Selection Using Machine Learning Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Security Assurance for System-on-Chip Designs With Untrusted IPs.
IEEE Trans. Inf. Forensics Secur., 2017

Guest Editorial: Security Challenges in the IoT Regime.
J. Hardw. Syst. Secur., 2017

Post-Silicon Validation in the SoC Era: A Tutorial Introduction.
IEEE Des. Test, 2017

Challenges and Trends in Modern SoC Design Verification.
IEEE Des. Test, 2017

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Transportation security in the era of autonomous vehicles: Challenges and practice.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Extensibility in Automotive Security: Current Practice and Challenges: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

System-on-chip security assurance for IoT devices: Cooperations and conflicts.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

MUTARCH: Architectural diversity for FPGA device and IP security.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape.
IEEE Trans. Multi Scale Comput. Syst., 2016

The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction.
IEEE Des. Test, 2016

Security validation in IoT space.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Security challenges in mobile and IoT systems.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Robust bitstream protection in FPGA-based systems through low-overhead obfuscation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Technical demonstration session: Software toolflow for FPGA bitstream obfuscation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Protocol-guided analysis of post-silicon traces under limited observability.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

The power play: Security-energy trade-offs in the IoT regime.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Multilevel design understanding: from specification to logic (invited paper).
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Validating scheduling transformation for behavioral synthesis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting transaction level models for observability-aware post-silicon test generation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting design-for-debug for flexible SoC security architecture.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Guest Editors' Introduction: Wearables, Implants, and Internet of Things.
IEEE Trans. Multi Scale Comput. Syst., 2015

Security Policy Enforcement in Modern SoC Designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A Flexible Architecture for Systematic Implementation of SoC Security Policies.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Transaction Flows and Executable Models: Formalization and Analysis of Message passing Protocols.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Correctness and security at odds: post-silicon validation of modern SoC designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis.
Proceedings of the Proceedings Twelfth International Workshop on the ACL2 Theorem Prover and its Applications, 2014

Mechanical Certification of Loop Pipelining Transformations: A Preview.
Proceedings of the Interactive Theorem Proving - 5th International Conference, 2014

Efficient trace signal selection using augmentation and ILP techniques.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Equivalence checking for function pipelining in behavioral synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Scalable Certification Framework for Behavioral Synthesis Front-End.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Specification and Verification of Concurrent Programs Through Refinements.
J. Autom. Reason., 2013

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.
J. Electron. Test., 2013

Equivalence checking for compiler transformations in behavioral synthesis.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Scalable trace signal selection using machine learning.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Preface.
Proceedings of the Formal Methods in Computer-Aided Design, 2013

Handling design and implementation optimizations in equivalence checking for behavioral synthesis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Introduction to special section on verification challenges in the concurrent world.
ACM Trans. Design Autom. Electr. Syst., 2012

Equivalence checking for behaviorally synthesized pipelines.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
The Right Tools for the Job: Correctness of Cone of Influence Reduction Proved Using ACL2 and HOL4.
J. Autom. Reason., 2011

A Unified Formal Framework for Analyzing Functional and Speed-path Properties.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

2010
Innovative practices session 7C: Verification and testing challenges in high-level synthesis.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Modeling and verification of industrial flash memories.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Optimizing equivalence checking for behavioral synthesis.
Proceedings of the Design, Automation and Test in Europe, 2010

Scalable Techniques for Formal Verification.
Springer, ISBN: 978-1-4419-5997-3, 2010

2009
Integrating external deduction tools with ACL2.
J. Appl. Log., 2009

Connecting pre-silicon and post-silicon verification.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Formal Verification for High-Assurance Behavioral Synthesis.
Proceedings of the Automated Technology for Verification and Analysis, 2009

2008
Efficient execution in an automated reasoning environment.
J. Funct. Program., 2008

A Mechanical Analysis of Program Verification Strategies.
J. Autom. Reason., 2008

Abstraction as a Practical Debugging Tool.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Mechanized Information Flow Analysis through Inductive Assertions.
Proceedings of the Formal Methods in Computer-Aided Design, 2008

2007
Combining Theorem Proving with Model Checking through Predicate Abstraction.
IEEE Des. Test Comput., 2007

A Survey of Hybrid Techniques for Functional Verification.
IEEE Des. Test Comput., 2007

Mechanized Certification of Secure Hardware Designs.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

A Mechanized Refinement Framework for Analysis of Custom Memories.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
Verification Condition Generation Via Theorem Proving.
Proceedings of the Logic for Programming, 2006

Quantification in tail-recursive function definitions.
Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, 2006

2004
Proof Styles in Operational Semantics.
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

Deductive Verification of Pipelined Machines Using First-Order Quantification.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004


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