Sandhya Koteshwara

Orcid: 0000-0003-3182-219X

According to our database1, Sandhya Koteshwara authored at least 19 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Position Paper: From Confidential Computing to Zero Trust, Come Along for the (Bumpy?) Ride.
Proceedings of the 13th International Workshop on Hardware and Architectural Support for Security and Privacy, 2024

STRonG: System Topology Risk Analysis on Graphs.
Proceedings of the 24th IEEE International Symposium on Cluster, 2024

S2TAR: Shared Secure Trusted Accelerators with Reconfiguration for Machine Learning in the Cloud.
Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024

2023
AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021
Security Risk Assessment of Server Hardware Architectures Using Graph Analysis.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure.
J. Hardw. Syst. Secur., 2020

Analysis and Hardware Optimization of Lattice Post-Quantum Cryptography Workloads.
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

Performance Optimization of Lattice Post-Quantum Cryptographic Algorithms on Many-Core Processors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019
Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2019

ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019

2018
Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design.
IEEE Trans. Inf. Forensics Secur., 2018

Incremental-Precision Based Feature Computation and Multi-Level Classification for Low-Energy Internet-of-Things.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Energy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and Multi-Level Classification.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Comparative Study of Authenticated Encryption Targeting Lightweight IoT Applications.
IEEE Des. Test, 2017

Hierarchical functional obfuscation of integratec circuits using a mode-based approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA implementation and comparison of AES-GCM and Deoxys authenticated encryption schemes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Functional encryption of integrated circuits by key-based hybrid obfuscation.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

Performance comparison of AES-GCM-SIV and AES-GCM algorithms for authenticated encryption on FPGA platforms.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Mode-based Obfuscation using Control-Flow Modifications.
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016


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