Sandeep Pande
According to our database1,
Sandeep Pande
authored at least 14 papers
between 2010 and 2019.
Collaborative distances:
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Bibliography
2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
J. Low Power Electron., 2018
2017
Rapid application prototyping for hardware modular spiking neural network architectures.
Neural Comput. Appl., 2017
2013
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
IEEE Trans. Parallel Distributed Syst., 2013
Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Parallel Comput., 2013
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network.
Neural Process. Lett., 2013
2012
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.
Neural Networks, 2012
Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
2011
Genet. Program. Evolvable Mach., 2011
Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures.
Proceedings of the NCTA 2011, 2011
Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2011, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2010