Sandeep Mishra
Orcid: 0000-0002-5893-9243
According to our database1,
Sandeep Mishra
authored at least 31 papers
between 2016 and 2025.
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Bibliography
2025
IEEE Trans. Image Process., 2025
2024
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine.
Integr., 2024
CoRR, 2024
Proceedings of the Workshop on Knowledge-infused Learning co-located with 30th ACM SIGKDD Conference on Knowledge Discovery and Data Mining (KDD), 2024
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024
2023
A comprehensive review of quantum random number generators: concepts, classification and the origin of randomness.
Quantum Inf. Process., December, 2023
Use of Internet of Things in the context of execution of smart city applications: a review.
Discov. Internet Things, December, 2023
Quantum Inf. Process., July, 2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
2022
Attainable and usable coherence in X states over Markovian and non-Markovian channels.
Quantum Inf. Process., 2022
2021
IET Circuits Devices Syst., 2021
2020
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
J. Inf. Sci. Eng., 2020
Low-power content addressable memory design using two-layer P-N match-line control and sensing.
Integr., 2020
IET Comput. Digit. Tech., 2020
Proceedings of the 31st British Machine Vision Conference 2020, 2020
2019
Comparing coherence measures for <i>X</i> states: Can quantum states be ordered based on quantum coherence?
Quantum Inf. Process., 2019
Low discharge precharge free matchline structure for energy-efficient search using CAM.
Integr., 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
2018
IEEE Trans. Geosci. Remote. Sens., 2018
Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory.
IEEE Trans. Consumer Electron., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016