Sandeep Miryala
Orcid: 0000-0003-1277-1745
According to our database1,
Sandeep Miryala
authored at least 26 papers
between 2011 and 2023.
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Bibliography
2023
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2020
A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process.
Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020
2017
Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch.
IET Circuits Devices Syst., 2017
2016
Proceedings of the 13th International Conference on Synthesis, 2016
2015
Microprocess. Microsystems, 2015
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
PhD thesis, 2014
Microelectron. J., 2014
J. Electron. Test., 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices.
Proceedings of the 14th Latin American Test Workshop, 2013
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Exploration of different implementation styles for graphene-based reconfigurable gates.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Efficient nanoscale VLSI standard cell library characterization using a novel delay model.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011