Sandeep Koranne

According to our database1, Sandeep Koranne authored at least 20 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2023
Design of Hardware Accelerators to Compute Parametric Capacitance Tables.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2015
DÉJÀ VU: An Entropy Reduced Hash Function for VLSI Layout Databases.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Design and Analysis of Silicon Photonics Wave Guides Using Symbolic Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
Constructing small-signal equivalent impedances using ellipsoidal norms.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
Analysis of very large resistive networks using low distortion embedding.
Proceedings of the International Symposium on Quality Electronic Design, 2013

2011
Entropy-reduced hashing for physical IP management.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
An innovative method to automate the waiver of IP-level DRC violations.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2004
A Note on System-on-Chip Test Scheduling Formulation.
J. Electron. Test., 2004

A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003
Design of reconfigurable access wrappers for embedded core based SoC test.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Formulating SoC test scheduling as a network transportation problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm.
J. Electron. Test., 2002

On Test Scheduling for Core-Based SOCs.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

On the Use of k-tuples for SoC Test Schedule Representation.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Formulation of SOC Test Scheduling as a Network Transportation Problem.
Proceedings of the 2002 Design, 2002

2001
A P1500 Compliant Programable BistShell for Embedded Memories.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

On automatic analysis of geometrically proximate nets in VSLI layout.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1999
A Distributed Algorithm for the Estimation of Average Switching Activity in Combinational Circuits.
Proceedings of the High-Performance Computing and Networking, 7th International Conference, 1999

A Distributed Algorithm for k-way Graph Partitioning.
Proceedings of the 25th EUROMICRO '99 Conference, 1999


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