Sandeep Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Built in self test (BIST) for RSFQ circuits.

[BibT_eX]

[DOI]

Yunkun Lin

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm<sup>2</sup> Active Area in 12nm FinFET.

[BibT_eX]

[DOI]

Qiaochu Zhang

Shiyu Su

Baishakhi Rani Biswas

Mike Shuo-Wei Chen

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Predictive Testing for Aging in SRAMs and Mitigation.

[BibT_eX]

[DOI]

Yunkun Lin

Proceedings of the IEEE International Test Conference, 2024

A Novel Multi-Objective Optimization Framework for Analog Circuit Customization.

[BibT_eX]

[DOI]

Mutian Zhu

Mohsen Hassanpourghadi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Design for testability (DFT) for RSFQ circuits.

[BibT_eX]

[DOI]

Yunkun Lin

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022

Methods for testing path delay and static faults in RSFQ circuits.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Memristor-Specific Failures: New Verification Methods and Emerging Test Problems.

[BibT_eX]

[DOI]

Baishakhi Rani Biswas

Vennela Chowdary Nekkanti

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Fault-coverage Maximizing March Tests for Memory Testing.

[BibT_eX]

[DOI]

Aditya Rajendra Pharande

Proceedings of the IEEE International Test Conference, 2022

2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.

[BibT_eX]

[DOI]

Juzheng Liu

Shiyu Su

Meghna Madhusudan

Mohsen Hassanpourghadi

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks.

[BibT_eX]

[DOI]

Soowang Park

Jae-Won Nam

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Aging-resilient SRAM design: an end-to-end framework.

[BibT_eX]

[DOI]

Xuan Zuo

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Data-driven fault model development for superconducting logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

2019

Collaborative circuit designs using the CRAFT repository.

[BibT_eX]

[DOI]

Rafael Ferreira da Silva

Ian J. Taylor

Karan Vahi

Future Gener. Comput. Syst., 2019

A New Method for Software Test Data Generation Inspired by D-algorithm.

[BibT_eX]

[DOI]

Jianwei Zhang

William G. J. Halfond

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuits.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable).

[BibT_eX]

[DOI]

Soowang Park

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Secure Gateway for Enabling ASIC Design Collaborations.

[BibT_eX]

[DOI]

Rafael Ferreira da Silva

Proceedings of the 11th International Workshop on Science Gateways, 2019

Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

2017

Asymmetric sizing: An effective design approach for SRAM cells against BTI aging.

[BibT_eX]

[DOI]

Xuan Zuo

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Accelerating Circuit Realization via a Collaborative Gateway of Innovations.

[BibT_eX]

[DOI]

Ian J. Taylor

Adam Brinckman

Ewa Deelman

Rafael Ferreira da Silva

Proceedings of the 9th International Workshop on Science Gateways, 2017

Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Process variation oriented delay testing of SRAMs.

[BibT_eX]

[DOI]

Xuan Zuo

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

SRAM yield-per-area optimization under spatially-correlated process variation.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Using hardware testing approaches to improve software testing: Undetectable mutant identification.

[BibT_eX]

[DOI]

Jianwei Zhang

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Yield estimation and statistical design of memristor cross-point memory systems.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

A multi-layered methodology for defect-tolerance of datapath modules in processors.

[BibT_eX]

[DOI]

Hsunwei Hsiung

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

PPB: Partially-working processors binning for maximizing wafer utilization.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Analysis and optimization of soft error tolerance strategies for real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014

Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Optimizing redundancy design for chip-multiprocessors for flexible utility functions.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SRAM Array Yield Estimation under Spatially-Correlated Process Variation.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Optimal Redundancy Designs for CNFET-Based Circuits.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

A Resizing Method to Minimize Effects of Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors.

[BibT_eX]

[DOI]

Yue Gao

Proceedings of the Design, Automation and Test in Europe, 2013

Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

A New March Test for Process-Variation Induced Delay Faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

A design flow to maximize yield/area of physical devices via redundancy.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Theory of redundancy for logic circuits to maximize yield/area.

[BibT_eX]

[DOI]

Shahin Nazarian

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Towards systematic roadmaps for networked systems.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Workshop on Hot Topics in Networks, 2012

A systematic methodology to improve yield per area of highly-parallel CMPs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Salvaging chips with caches beyond repair.

[BibT_eX]

[DOI]

Hsunwei Hsiung

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Efficient Trojan Detection via Calibration of Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

A novel software-based defect-tolerance approach for application-specific embedded systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A new circuit simplification method for error tolerant applications.

[BibT_eX]

[DOI]

Doochul Shin

Proceedings of the Design, Automation and Test in Europe, 2011

On Generating Vectors for Accurate Post-Silicon Delay Characterization.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Modeling the interactions between MAC and higher layer: A systematic approach to generate high-level scenarios from MAC-layer scenarios.

[BibT_eX]

[DOI]

Shamim Begum

ACM Trans. Model. Comput. Simul., 2010

Design and test of latch-based circuits to maximize performance, yield, and delay test quality.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Approximate logic synthesis for error tolerant applications.

[BibT_eX]

[DOI]

Doochul Shin

Proceedings of the Design, Automation and Test in Europe, 2010

Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Threshold Testing: Improving Yield for Nanoscale VLSI.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Efficient Scheduling of Path Delay Tests for Latch-Based Circuits.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Modeling and test generation for worst-case performance evaluation of MAC protocols for wireless ad hoc networks.

[BibT_eX]

[DOI]

Shamim Begum

Proceedings of the 17th Annual Meeting of the IEEE/ACM International Symposium on Modelling, 2009

Tolerance of performance degrading faults for effective yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation.

[BibT_eX]

[DOI]

Jung-Yup Kang

Jean-Luc Gaudiot

IEEE Trans. Computers, 2008

An Industrial Case Study of Sticky Path-Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

On Accelerating Path Delay Fault Simulation of Long Test Sequences.

[BibT_eX]

[DOI]

Ramesh Sharma

Proceedings of the 2008 IEEE International Test Conference, 2008

Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

Characterization of granularity and redundancy for SRAMs for optimal yield-per-area.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Multi-Vector Tests: A Path to Perfect Error-Rate Testing.

[BibT_eX]

[DOI]

Shideh Shahidi

Proceedings of the Design, Automation and Test in Europe, 2008

Matrix Inversion on a PIM (Processor-in-Memory).

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Science and Software Engineering, 2008

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults.

[BibT_eX]

[DOI]

Arani Sinha

Proceedings of the 17th IEEE Asian Test Symposium, 2008

A Re-design Technique for Datapath Modules in Error Tolerant Applications.

[BibT_eX]

[DOI]

Doochul Shin

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Performance Analysis of Wireless MAC Protocols Using a Search Based Framework.

[BibT_eX]

[DOI]

Shamim Begum

Proceedings of the 15th International Symposium on Modeling, 2007

Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

LT-RTPG: a new test-per-scan BIST TPG for low switching activity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A theory of Error-Rate Testing.

[BibT_eX]

[DOI]

Shideh Shahidi

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

STAX: statistical crosstalk target set compaction.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Diagnosis of delay faults due to resistive bridges, delay variations and defects.

[BibT_eX]

[DOI]

Lei Wang

Proceedings of the 15th Asian Test Symposium, 2006

Test Generation for Weak Resistive Bridges.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

FOTG: fault-oriented stress testing of IP multicast.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2005

Multiple tests for each gate delay fault: higher coverage and lower test application cost.

[BibT_eX]

[DOI]

Shirin Ebrahimi-Taghizadeh

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

TCP vs. TCP: a systematic study of adverse impact of short-lived TCP flows on long-lived TCP flows.

[BibT_eX]

[DOI]

Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005

A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects.

[BibT_eX]

[DOI]

Wichian Sirisaengtaksin

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Threshold testing: Covering bridging and other realistic faults.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Selection of Paths for Delay Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

The STRESS method for boundary-point performance analysis of end-to-end multicast timer-suppression mechanisms.

[BibT_eX]

[DOI]

Deborah Estrin

IEEE/ACM Trans. Netw., 2004

A framework for systematic evaluation of multicast congestion control protocols.

[BibT_eX]

[DOI]

Karim Seada

IEEE J. Sel. Areas Commun., 2004

Defect and Error Tolerance in the Presence of Massive Numbers of Defects.

[BibT_eX]

[DOI]

T. M. Mak

IEEE Des. Test Comput., 2004

Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture.

[BibT_eX]

[DOI]

Jung-Yup Kang

Jean-Luc Gaudiot

Proceedings of the 3rd International IEEE Computer Society Computational Systems Bioinformatics Conference, 2004

Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.

[BibT_eX]

[DOI]

Lei Wang

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets.

[BibT_eX]

[DOI]

Wichian Sirisaengtaksin

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Efficient Identification of Crosstalk Induced Slowdown Targets.

[BibT_eX]

[DOI]

Shahin Nazarian

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Benefits of a SoC-Specific Test Methodology.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Analyzing Crosstalk in the Presence of Weak Bridge Defects.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Test Generation for Maximizing Ground Bounce Considering Circuit Delay.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Generating Complete and Optimal March Tests for Linked Faults in Memories.

[BibT_eX]

[DOI]

Sultan M. Al-Harbi

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets.

[BibT_eX]

[DOI]

Nabil M. Abdulrazzaq

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.

[BibT_eX]

[DOI]

Arani Sinha

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Designing Multiple Scan Chains for Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002

An automatic test pattern generator for minimizing switching activity during scan testing activity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

DS-LFSR: a BIST TPG for low switching activity.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Analytical models for crosstalk excitation and propagation in VLSI circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

TA-PSV - Timing Analysis for Partially Specified Vectors.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

XIDEN: Crosstalk Target Identification Framework.

[BibT_eX]

[DOI]

Shahin Nazarian

Hang Huang

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Accurate and Efficient Static Timing Analysis with Crosstalk.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology.

[BibT_eX]

[DOI]

Wichian Sirisaengtaksin

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Introducing redundant computations in RTL data paths for reducing BIST resources.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

Path delay fault diagnosis in combinational circuits with implicitfault enumeration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

An Efficient Methodology for Generating Optimal and Uniform March Tests.

[BibT_eX]

[DOI]

Sultan M. Al-Harbi

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Switch-level delay test of domino logic circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Crosstalk test generation on pseudo industrial circuits: a case study.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Exact fault simulation for systems on Silicon that protects each core's intellectual property.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A New Gate Delay Model for Simultaneous Switching and Its Applications.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Novel Test Pattern Generators for Pseudoexhaustive Testing.

[BibT_eX]

[DOI]

Rajagopalan Srinivasan

IEEE Trans. Computers, 2000

BIST TPG for Combinational Cluster Interconnect Testing at Board Level.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study.

[BibT_eX]

[DOI]

Hugo Cheung

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Systematic Testing of Protocol Robustness: Case Studies on Mobile IP and MARS.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 27th Conference on Local Computer Networks, 2000

Test generation for path-delay faults in one-dimensional iterative logic arrays.

[BibT_eX]

[DOI]

Nabil M. Abdulrazzaq

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Systematic testing of multicast routing protocols: analysis of forward and backward search techniques.

[BibT_eX]

[DOI]

Deborah Estrin

Proceedings of the Proceedings Ninth International Conference on Computer Communications and Networks, 2000

Systematic Performance Evaluation of Multipoint Protocols.

[BibT_eX]

Proceedings of the Formal Techniques for Distributed System Development, 2000

BIST TPG for SRAM cluster interconnect testing at board level.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Test generation for crosstalk-induced faults: framework and computational result.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A new framework for static timing analysis, incremental timing refinement, and timing simulation.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Test Generation for Ground Bounce in Internal Logic Circuitry.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Switch-level delay test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Test generation for crosstalk-induced delay in integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Validation and test generation for oscillatory noise in VLSI interconnects.

[BibT_eX]

[DOI]

Arani Sinha

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

Bounds on pseudoexhaustive test lengths.

[BibT_eX]

[DOI]

Rajagopalan Srinivasan

IEEE Trans. Very Large Scale Integr. Syst., 1998

ATPG for Heat Dissipation Minimization During Test Application.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Estimation of BIST Resources During High-Level Synthesis.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Allocation Techniques for Reducing BIST Area Overhead of Data Paths.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags.

[BibT_eX]

[DOI]

Sultan M. Al-Harbi

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A new path-oriented effect-cause methodology to diagnose delay failures.

[BibT_eX]

[DOI]

Yuan-Chieh Hsu

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Test generation in VLSI circuits for crosstalk noise.

[BibT_eX]

[DOI]

Weiyu Chen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fault-oriented Test Generation for Multicast Routing Protocol Design.

[BibT_eX]

Deborah Estrin

Proceedings of the Formal Description Techniques and Protocol Specification, 1998

Process Variations and their Impact on Circuit Operation.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Scheduling and Module Assignment for Reducing Bist Resources.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Introducing Redundant Computations in a Behavior for Reducing BIST Resources.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing.

[BibT_eX]

[DOI]

Yuan-Chieh Hsu

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

High Quality Robust Tests for Path Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analysis of Ground Bounce in Deep Sub-Micron Circuits.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

DS-LFSR: A New BIST TPG for Low Heat Dissipation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs.

[BibT_eX]

[DOI]

Weiyu Chen

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

BIST TPG for faults in system backplanes.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

ATPG for Heat Dissipation Minimization During Scan Testing.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.

[BibT_eX]

[DOI]

Yuan-Chieh Hsu

IEEE Trans. Computers, 1996

Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa.

[BibT_eX]

[DOI]

Dhiraj K. Pradhan

IEEE Trans. Computers, 1996

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms.

[BibT_eX]

[DOI]

Chih-Ang Chen

IEEE Trans. Computers, 1996

Fault macromodeling and a testing strategy for opamps.

[BibT_eX]

[DOI]

Chen-Yang Pan

Kwang-Ting Cheng

J. Electron. Test., 1996

Delay Fault Testing: How Robust are Our Models?

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Process-Aggravated Noise (PAN): New Validation and Test Problems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Lower Bounds on Test Resources for Scheduled Data Flow Graphs.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts.

[BibT_eX]

[DOI]

Chih-Ang Chen

Proceedings of the 33st Conference on Design Automation, 1996

1995

Test embedding with discrete logarithms.

[BibT_eX]

[DOI]

Mody Lempel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

Weighted random robust path delay testing of synthesized multilevel circuits.

[BibT_eX]

[DOI]

Weili Wang

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

A comprehensive fault macromodel for opamps.

[BibT_eX]

[DOI]

Chen-Yang Pan

Kwang-Ting Cheng

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Random pattern testable logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Low Cost BIST Methodology and Associated Novel Test Pattern Generator.

[BibT_eX]

[DOI]

Sen-Pin Lin

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

BIST Test Pattern Generators for Stuck-Open and Delay Testing.

[BibT_eX]

[DOI]

Chih-Ang Chen

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Clock Grouping: A Low Cost DFT Methodology for Delay Testing.

[BibT_eX]

[DOI]

Wen-Chang Fang

Proceedings of the 31st Conference on Design Automation, 1994

1993

Novel Test Pattern Generators for Pseudo-Exhaustive Testing.

[BibT_eX]

[DOI]

Rajagopalan Srinivasan