Sandeep Chandran

According to our database, Sandeep Chandran authored at least 14 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties.

Amrutha Benny, Sandeep Chandran, Rajshekar Kalayappan, Ramchandra Phawade, Piyush P. Kurur

Proceedings of the Runtime Verification - 24th International Conference, 2024

CASH: Criticality-Aware Split Hybrid L1 Data Cache.

Shruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, Sandeep Chandran

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

On Decomposing Complex Test Cases for Efficient Post-silicon Validation.

C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Dynamic Ineffectuality-based Clustered Architectures.

Rajshekar Kalayappan, Sandeep Chandran

CoRR, 2023

SANNA: Secure Acceleration of Neural Network Applications.

Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2019

DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring.

Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation.

Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Area-Aware Cache Update Trackers for Postsilicon Validation.

Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Generic Implementation of Barriers Using Optical Interconnects.

Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Extending trace history through tapered summaries in post-silicon validation.

Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects.

Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi

CoRR, 2015

2014

Architectural Support for Handling Jitterin Shared Memory Based Parallel Applications.

Sandeep Chandran, Prathmesh Kallurkar, Parul Gupta, Smruti R. Sarangi

IEEE Trans. Parallel Distributed Syst., 2014

2013

Space sensitive cache dumping for post-silicon validation.

Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda

Proceedings of the Design, Automation and Test in Europe, 2013

2002

Heuristic random optimizer-version II.

Sandeep Chandran, R. Russell Rhinehart

Proceedings of the American Control Conference, 2002