Samvel K. Shoukourian

Affiliations:
  • Yerevan State University


According to our database1, Samvel K. Shoukourian authored at least 36 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Analytics for AI Related Applications of Multidimensional Multitape Finite Automata.
Proceedings of the Electronics, Communications and Networks, 2023

2021
Some Results on Regular Events for Multitape Finite Automata: A Preliminary Report.
Bull. EATCS, 2021

2020
Memory Physical Aware Multi-Level Fault Diagnosis Flow.
IEEE Trans. Emerg. Top. Comput., 2020

Polynomial algorithm for equivalence problem of deterministic multitape finite automata.
Theor. Comput. Sci., 2020

2019
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Innovative Practices on In-System Test and Reliability of Memories.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Armenia: Communicating to World Community in Electronic Test and Design.
Proceedings of the IEEE International Test Conference, 2019

Memory FIT Rate Mitigation Technique for Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2019

2018
Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2018

2017
Experimental study on Hamming and Hsiao codes in the context of embedded applications.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Automated flow for test pattern creation for IPs in SoC.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

An efficient testing methodology for embedded flash memories.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Securing test infrastructure of system-on-chips.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Overview study on fault modeling and test methodology development for FinFET-based memories.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

An efficient approach for memory repair by reducing the number of spares.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

A power based memory BIST grouping methodology.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Extending fault periodicity table for testing faults in memories under 20nm.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
An effective solution for building memory BIST infrastructure based on fault periodicity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An efficient fault diagnosis and localization algorithm for Successive-Approximation Analog to Digital Converters.
Proceedings of the East-West Design & Test Symposium, 2013

Impact of process variations on read failures in SRAMs.
Proceedings of the East-West Design & Test Symposium, 2013

Application of defect injection flow for fault validation in memories.
Proceedings of the East-West Design & Test Symposium, 2013

2012
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Symmetry Measure for Memory Test and Its Application in BIST Optimization.
J. Electron. Test., 2011

Generic BIST architecture for testing of content addressable memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Robust Solution for Embedded Memory Test and Repair.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
The Equivalence Problem of Deterministic Multitape Finite Automata: A New Proof of Solvability Using a Multidimensional Tape.
Proceedings of the Language and Automata Theory and Applications, 2010

2009
An approach for formal verification of business processes.
Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009

2008
The equivalence problem of multidimensional multitape automata.
J. Comput. Syst. Sci., 2008

2006
Alternative Combination of Processes.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

2004
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure.
IEEE Des. Test Comput., 2004

A Methodology for Design and Evaluation of Redundancy Allocation Algorithms.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2003
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield.
IEEE Des. Test Comput., 2003

2001
An Approach for Evaluation of Redunancy Analysis Algorithms.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

1999
An Approach for Access Differentiation Design in Medical Distributed Applications Built on Databases.
Proceedings of the Medical Informatics Europe '99, Proceedings, Ljubljana, Slovenia, 1999

1998
A Unified Design Methodology for Offline and Online Testing.
IEEE Des. Test Comput., 1998

1995
An approach for system tests design and its application.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995


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