Samuele Germiniani

According to our database, Samuele Germiniani authored at least 15 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs.

Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola

J. Electron. Test., April, 2024

Enhancing Safety and Privacy in Industry 4.0: The ICE Laboratory Case Study.

Federico Cunico, Stefano Aldegheri, Andrea Avogaro, Michele Boldo, Nicola Bombieri, Luigi Capogrosso, Ariel Caputo, Damiano Carra, Stefano Centomo, Dong Seon Cheng, Ettore Cinquetti, Marco Cristani, Mirco De Marchi, Florenc Demrozi, Marco Emporio, Franco Fummi, Luca Geretti, Samuele Germiniani, Andrea Giachetti, Federico Girella, Enrico Martini, Gloria Menegaz, Niek Muijs, Federica Paci, Marco Panato, Graziano Pravadelli, Elisa Quintarelli, Ilaria Siviero, Silvia Francesca Storti, Carlo Tadiello, Cristian Turetta, Tiziano Villa, Nicola Zannone, Davide Quaglia

IEEE Access, 2024

Invited Talk: Pros and Cons of Assertion Mining.

Samuele Germiniani, Daniele Nicoletti, Graziano Pravadelli

Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Mining signal temporal logic specifications for hybrid systems.

Daniele Nicoletti, Samuele Germiniani, Graziano Pravadelli

Proceedings of the Forum on Specification & Design Languages, 2024

2023

Exploiting assertions mining and fault analysis to guide RTL-level approximation.

Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Automatic Generation of Assertions for Detection of Firmware Vulnerabilities Through Alignment of Symbolic Sequences.

Samuele Germiniani, Alessandro Danese, Graziano Pravadelli

IEEE Trans. Emerg. Top. Comput., 2022

HARM: A Hint-Based Assertion Miner.

Samuele Germiniani, Graziano Pravadelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions.

Samuele Germiniani, Graziano Pravadelli

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Assertion-aware approximate computing design exploration on behavioral models.

Alberto Bosio, Moreno Bragaglio, Samuele Germiniani, Samuele Mori, Graziano Pravadelli, Marcello Traiola

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Risk Assessment and Prediction in Human-Robot Interaction Through Assertion Mining and Pose Estimation.

Michele Boldo, Nicola Bombieri, Mirco De Marchi, Luca Geretti, Samuele Germiniani, Graziano Pravadelli

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

2021

Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level.

Moreno Bragaglio, Samuele Germiniani, Graziano Pravadelli

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

System-level bug explanation through program slicing and instruction clusterization.

Moreno Bragaglio, Nicola Donatelli, Samuele Germiniani, Graziano Pravadelli

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

A containerized ROS-compliant verification environment for robotic systems.

Stefano Aldegheri, Nicola Bombieri, Samuele Germiniani, Federico Moschin, Graziano Pravadelli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

From Informal Specifications to an ABV Framework for Industrial Firmware Verification.

Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli

Proceedings of the VLSI-SoC: Design Trends, 2020

MIST: monitor generation from informal specifications for firmware verification.

Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020