Samuel Palermo

Orcid: 0000-0002-6555-1474

According to our database1, Samuel Palermo authored at least 105 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET.
IEEE J. Solid State Circuits, September, 2024

A Radiation-Hardened 15-22-GHz Frequency Synthesizer in 22-nm FinFET.
IEEE J. Solid State Circuits, September, 2024

Optical Interconnects Using Hybrid Integration of CMOS and Silicon-Photonic ICs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS.
IEEE Access, 2024

Comparisons of Metastability Impact in Time-Domain and Asynchronous SAR ADCs for Serial I/O Receivers.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

The Design of Wideband LNAs in 45nm SiGe BiCMOS.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024

2023
A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET.
IEEE J. Solid State Circuits, March, 2023

Spectral Ranking in Complex Networks Using Memristor Crossbars.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET.
IEEE J. Solid State Circuits, 2023

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels.
IEEE J. Solid State Circuits, 2023

A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

Gaussian Process for Nonlinear Regression via Memristive Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Memristor-based Offset Cancellation Technique in Analog Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Recurrent Neural Network Equalization for Wireline Communication Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads.
Proceedings of the High Performance Computing - 37th International Conference, 2022

Automated Tuning for Silicon Photonic Filters.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A Mathematical Analysis of Wire Resistance Problem in Memristor Crossbars.
Proceedings of the 19th International SoC Design Conference, 2022

Analog Acceleration of the Power Method using Memristor Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

SEE Sensitivity of a 16GHz LC-Tank VCO in a 22nm FinFET Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
Analog Solutions of Discrete Markov Chains via Memristor Crossbars.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

External Modulator-Based Automatic Tuning of Reconfigurable Silicon Photonic 4<sup>th</sup>-Order APF-based Pole/Zero Filters.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

A Power-Efficient 20-35 GHz MZM Driver with Programmable Linearizer in 28nm CMOS.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

Design of Tunable Analog Filters Using Memristive Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 40Gb/s Linear Redriver with Multi-Band Equalization in 130nm SiGe BiCMOS.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021

2020
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques.
IEEE J. Solid State Circuits, 2020

A 22 Gb/s Directly Modulated Optical Injection-Locked Quantum-Dot Microring Laser Transmitter with Integrated CMOS Driver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2019

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

A Directly Modulated Quantum Dot Microring Laser Transmitter with Integrated CMOS Driver.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper).
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Guest Editorial 2017 IEEE Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2018

A 14 Gb/s Directly Modulated Hybrid Microring Laser Transmitter.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A Fully-integrated Multi-λ Hybrid DML Transmitter.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter.
Proceedings of the 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018

2017
A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS.
IEEE J. Solid State Circuits, 2017

A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.
IEEE J. Solid State Circuits, 2017

A 40Gb/s PAM4 optical DAC silicon microring resonator modulator transmitter.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Session 29 overview: Optical- and electrical-link innovations.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.
IEEE J. Solid State Circuits, 2016

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization.
IEEE J. Solid State Circuits, 2016

CMOS ADC-based receivers for high-speed electrical and optical links.
IEEE Commun. Mag., 2016

2015
A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS.
IEEE J. Solid State Circuits, 2015

A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique.
Proceedings of the Symposium on VLSI Circuits, 2015

25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Energy efficiency comparisons of NRZ and PAM4 modulation for ring-resonator-based silicon photonic links.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

An input pole tuned switching equalization scheme for high-speed serial links.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

DWDM nanophotonic interconnects: toward terabit/s chip-scale serial link.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Adaptively-tunable RF photonic filters.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications.
IEEE J. Solid State Circuits, 2014

An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning.
IEEE J. Solid State Circuits, 2014

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014

An Energy-Efficient Silicon Microring Resonator-Based Photonic Transmitter.
IEEE Des. Test, 2014

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A 15b, Sub-10ps resolution, low dead time, wide range two-stage TDC.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

10 Gb/s adaptive receive-side near-end and far-end crosstalk cancellation circuitry.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A single parity check forward error correction method for high speed I/O.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Sequential Correlated Level Shifting: A Switched-Capacitor Approach for High-Accuracy Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS.
IEEE J. Solid State Circuits, 2013

A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013

A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier.
IEEE J. Solid State Circuits, 2013

LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

A TDC-based front-end for rapid impedance spectroscopy.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

High-speed wireline timing recovery & PLLs.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter.
Microelectron. J., 2012

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.
IEEE J. Solid State Circuits, 2012

Digital-Assisted Asynchronous Compressive Sensing Front-End.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links.
J. Electr. Comput. Eng., 2011

Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Power Efficiency Comparisons of Interchip Optical Interconnect Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Optical I/O Technology for Tera-Scale Computing.
IEEE J. Solid State Circuits, 2010

Optical technology for energy efficient I/O in high performance computing.
IEEE Commun. Mag., 2010

2008
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects.
IEEE J. Solid State Circuits, 2008

2007
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


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