Samuel Evain

According to our database, Samuel Evain authored at least 17 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.

Valentin Gherman, Samuel Evain, Bastien Giraud

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2014

Error Correction Schemes with Erasure Information for Fast Memories.

Samuel Evain, Valentin Savin, Valentin Gherman

J. Electron. Test., 2014

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.

Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Shadow-scan design with low latency overhead and in-situ slack-time monitoring.

Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman

Proceedings of the 19th IEEE European Test Symposium, 2014

2013

Memory Reliability Improvement Based on Maximized Error-Correcting Codes.

Valentin Gherman, Samuel Evain, Yannick Bonhomme

J. Electron. Test., 2013

Error-correction schemes with erasure information for fast memories.

Samuel Evain, Valentin Gherman

Proceedings of the 18th IEEE European Test Symposium, 2013

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.

Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Memory reliability improvements based on maximized error-correcting codes.

Valentin Gherman, Samuel Evain, Yannick Bonhomme

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Programmable extended SEC-DED codes for memory errors.

Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Generalized parity-check matrices for SEC-DED codes with fixed parity.

Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Error prediction based on concurrent self-test and reduced slack time.

Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Programmable restricted SEC codes to mask permanent faults in semiconductor memories.

Samuel Evain, Yannick Bonhomme, Valentin Gherman

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009

System-level hardware-based protection of memories against soft-errors.

Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme

Proceedings of the Design, Automation and Test in Europe, 2009

2007

NOC-centric Security of Reconfigurable SoC.

Jean-Philippe Diguet, Samuel Evain, Romain Vaslin, Guy Gogniat, Emmanuel Juin

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Efficient space-time noc path allocation based on mutual exclusion and pre-reservation.

Samuel Evain, Jean-Philippe Diguet

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

NoC Design Flow for TDMA and QoS Management in a GALS Context.

Samuel Evain, Jean-Philippe Diguet, Dominique Houzet

EURASIP J. Embed. Syst., 2006

Automated derivation of NoC Communication Specifications from Application Constraints.

Samuel Evain, Jean-Philippe Diguet, Milad El Khodary, Dominique Houzet

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006