Samiran Ganguly

Orcid: 0000-0002-6632-1574

According to our database1, Samiran Ganguly authored at least 17 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Connecting physics to systems with modular spin-circuits.
CoRR, 2024

Reconfigurable Stochastic Neurons Based on Strain Engineered Low Barrier Nanomagnets.
CoRR, 2024

Double magnetic tunnel junction based ∑Δ∑ hardware neuron.
Proceedings of the Device Research Conference, 2024

2023
A Deep Dive into the Computational Fidelity of High Variability Low Energy Barrier Magnet Technology for Accelerating Optimization and Bayesian Problems.
CoRR, 2023

Choose your tools carefully: A Comparative Evaluation of Deterministic vs. Stochastic and Binary vs. Analog Neuron models for Implementing Emerging Computing Paradigms.
CoRR, 2023

Roadmap for Unconventional Computing with Nanotechnology.
CoRR, 2023

2021
Analog Signal Processing Using Stochastic Magnets.
IEEE Access, 2021

2020
Temporal Memory with Magnetic Racetracks.
CoRR, 2020

Ultra-Compact, Scalable, Energy-Efficient $VO_{2}$ Insulator-Metal-Transition Oxide Based Spiking Neurons for Liquid State Machines.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Building Reservoir Computing Hardware Using Low Energy-Barrier Magnetics.
Proceedings of the International Conference on Neuromorphic Systems, 2020

2018
Hardware based Spatio-Temporal Neural Processing Backend for Imaging Sensors: Towards a Smart Camera.
CoRR, 2018

Reservoir Computing Based Neural Image Filters.
Proceedings of the IECON 2018, 2018

2017
Reservoir Computing using Stochastic p-Bits.
CoRR, 2017

2016
Spintronic device modeling and evaluation using modular approach to spintronics
PhD thesis, 2016

Evaluating Spintronic Devices Using The Modular Approach.
CoRR, 2016

2007
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
Design of Multi-bit SET Adder and Its Fault Simulation.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006


  Loading...