Samir Parikh

According to our database, Samir Parikh authored at least 9 papers between 2005 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology.

Jian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.

Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.

Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.

Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2010

2009

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2009

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A CMOS Image Sensor for DNA Microarrays.

Samir Parikh, P. Glenn Gulak, Paul Chow

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Designing an FPGA SoC Using a Standardized IP Block Interface.

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005