Sameh W. Asaad
Orcid: 0000-0001-5652-9892
According to our database1,
Sameh W. Asaad
authored at least 24 papers
between 1996 and 2024.
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Bibliography
2024
Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024
2023
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design.
Proceedings of the 29th Symposium on Operating Systems Principles, 2023
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2017
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2016
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
2015
Int. J. Parallel Program., 2015
Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
2014
A Fully Pipelined FPGA Architecture of a Factored Restricted Boltzmann Machine Artificial Neural Network.
ACM Trans. Reconfigurable Technol. Syst., 2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014
2013
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013
2012
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
2003
An innovative low-power high-performance programmable signal processor for digital communications.
IBM J. Res. Dev., 2003
Reducing instruction fetch energy with backwards branch control information and buffering.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
2000
VLSI Design, 2000
1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience.
Proceedings of the Field-Programmable Logic and Applications, 1998
1996
Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems. IROS 1996, 1996