Sambuddha Bhattacharya
According to our database1,
Sambuddha Bhattacharya
authored at least 18 papers
between 2003 and 2015.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2015
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids.
Proceedings of the 28th International Conference on VLSI Design, 2015
2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2008
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 41th Design Automation Conference, 2004
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Hierarchical extraction and verification of symmetry constraints for analog layout automation.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Integr., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003