Samar Abdi

According to our database1, Samar Abdi authored at least 41 papers between 2002 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Rapid design space exploration of multi-clock domain MPSoCs with hybrid prototyping.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

PFPSim: A Programmable Forwarding Plane Simulator.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016

2015
On improving the range of inductive proximity sensors for avionic applications.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems.
Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Balancing system availability and lifetime with dynamic hidden Markov models.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Automatic Generation of Transducer Models for Bus-Based MPSoC Design.
IEEE Trans. Computers, 2013

Early system level modeling of real-time applications on embedded platforms.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Early and Accurate Modeling of Streaming Embedded Applications.
Proceedings of the 39th Euromicro Conference on Software Engineering and Advanced Applications, 2013

pCache: An Observable L1 Data Cache Model for FPGA Prototyping of Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Hybrid prototyping of multicore embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Automated Generation of Custom Processor Core from C Code.
J. Electr. Comput. Eng., 2012

System level modeling of real-time embedded software.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Automatic TLM Generation for Early Validation of Multicore Systems.
IEEE Des. Test Comput., 2011

Automatic generation of transducer models for multicore system design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

2010
Embedded system environment: A framework for TLM-based design and prototyping.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Automatic generation of host-compiled timed TLMs for high level design.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Accurate timed RTOS model for transaction level modeling.
Proceedings of the Design, Automation and Test in Europe, 2010

TLM automation for multi-core design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Model Based Synthesis of Embedded Software.
J. Softw., 2009

Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support.
Proceedings of the Analysis, 2009

Hardware-dependent software synthesis for many-core embedded systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design.
EURASIP J. Embed. Syst., 2008

Cycle-approximate Retargetable Performance Estimation at the Transaction Level.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Interface synthesis for heterogeneous multi-core systems from transaction level models.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Automatic SystemC TLM generation for custom communication platforms.
Proceedings of the 25th International Conference on Computer Design, 2007

Automatic TLM generation for C-Based MPSoC design.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006
Verification of System Level Model Transformations.
Int. J. Parallel Program., 2006

Transaction Routing and its Verification by Correct Model Transformations.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Design and implementation of transducer for ARM-TMS communication.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Functional Validation of System Level Static Scheduling.
Proceedings of the 2005 Design, 2005

A clustering technique to optimize hardware/software synchronization.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A formalism for functionality preserving system level transformations.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Model validation for mapping specification behaviors to processing elements.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Automatic generation of equivalent architecture model from functional specification.
Proceedings of the 41th Design Automation Conference, 2004

Automatic generation of bus functional models from transaction level models.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

On deriving equivalent architecture model from system specification.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Automatic communication refinement for system level design.
Proceedings of the 40th Design Automation Conference, 2003

2002
Automatic Model Refinement for Fast Architecture Exploration.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002


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