Saman Fröhlich

Orcid: 0000-0003-0917-5053

According to our database1, Saman Fröhlich authored at least 21 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
A Fully Fledged HDL Design Flow for In-Memory Computing with Approximation Support
PhD thesis, 2022

Parallel Computing of Graph-based Functions in ReRAM.
ACM J. Emerg. Technol. Comput. Syst., 2022

Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits.
it Inf. Technol., 2022

Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Polynomial Formal Verification of Approximate Functions.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Polynomial Formal Verification of Approximate Adders.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Generation of Verified Programs for In-Memory Computing.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

LiM-HDL: HDL-Based Synthesis for In-Memory Computing.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Depth Optimized Synthesis of Symmetric Boolean Functions.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Efficient machine learning through evolving combined deep neural networks.
Proceedings of the GECCO '20: Genetic and Evolutionary Computation Conference, 2020

2019
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Approximate Hardware Generation Using Formal Techniques.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
Towards Reversed Approximate Hardware Design.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Approximate hardware generation using symbolic computer algebra employing grobner basis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Error Bounded Exact BDD Minimization in Approximate Computing.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017


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