Saman Adham

According to our database, Saman Adham authored at least 22 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10¹² Write Endurance and Integrated Margin-Expansion Schemes.

Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm² and 3.78Mb/mm² Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.

Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019

A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering.

Shih-Lien Lu, Cheng-En Lee, Peter Noel, Saman Adham, Ted Wong, Jonathan Chang

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2014

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.

Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta

IEEE J. Solid State Circuits, 2014

A novel DFT architecture for 3DIC test, diagnosis and repair.

Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS^TM/3D ICs.

Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

The importance of DFX, a foundry perspective.

Saman Adham, Jonathan Chang, Hung-Jen Liao, John Hung, Ting-Hua Hsieh

Proceedings of the 2014 International Test Conference, 2014

2013

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim

Proceedings of the 2013 IEEE International Test Conference, 2013

2009

Improved Core Isolation and Access for Hierarchical Embedded Test.

Benoit Nadeau-Dostie, Saman Adham, Russell Abbott

IEEE Des. Test Comput., 2009

2004

A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.

Saman Adham, Benoit Nadeau-Dostie

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

2000

Comprehensive defect analysis and testability of current-mode logic circuits.

Saman Adham, Dhamin Al-Khalili, Côme Rozon, Douglas Racz

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Comparing defect coverage for current-mode logic and CMOS VLSI cells.

Côme Rozon, Dhamin Al-Khalili, Saman Adham, Douglas Racz

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Scan-based BIST fault diagnosis.

Yuejian Wu, Saman Adham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Linking diagnostic software to hardware self test in telecom systems.

Saman M. I. Adham, Ken Brough, Bruce Ecroyd, Stephen Foster, Paul Soong

IEEE Commun. Mag., 1999

Design For Testability Method for CML Digital Circuits.

Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham

Proceedings of the 1999 Design, 1999

1998

Test Reuse at System Level.

José M. Miranda, Scott Davidson, Peter Dziel, Saman Adham, Steve Millman

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.

Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1996

BIST Fault Diagnosis in Scan-Based VLSI Environments.

Yuejian Wu, Saman Adham

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique.

Saman Adham, Sanjay Gupta

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

A New Hardware Fault Insertion Scheme for System Diagnostics Verification.

Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Linking Diagnostic Software to Hardware Self Test in Telecom Systems.

Harry Hulvershorn, Paul Soong, Saman Adham

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995