Samah Mohamed Saeed
Orcid: 0000-0002-8107-3644
According to our database1,
Samah Mohamed Saeed
authored at least 45 papers
between 2010 and 2024.
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Bibliography
2024
Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
2023
Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
CoRR, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
An Attack on Quantum Circuits Based on the Error Rates of NISQ Systems and a Countermeasure.
Proceedings of the Silicon Valley Cybersecurity Conference - First Conference, 2020
A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
ACM Trans. Embed. Comput. Syst., 2019
ACM J. Emerg. Technol. Comput. Syst., 2019
2018
Proceedings of the International Conference on Computer-Aided Design, 2018
2017
IEEE Trans. Emerg. Top. Comput., 2017
A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications.
IEEE Des. Test, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
2014
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Des. Test, 2013
New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
IET Comput. Digit. Tech., 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010