Samad Sheikhaei

Orcid: 0000-0002-6221-7200

According to our database1, Samad Sheikhaei authored at least 36 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Local-to-Global Self-Supervised Representation Learning for Diabetic Retinopathy Grading.
CoRR, 2024

2023
Single-Inductor, Multiple-Input, Multiple-Output, DC-DC Converter Based on a New Software Zero-Current Switching Technique.
J. Circuits Syst. Comput., September, 2023

Image Interpolation Based on 2D-DWT with Novel Regularity-Preserving Algorithm Using RLS Adaptive Filters.
Int. J. Image Graph., September, 2023

A Novel, Software-Defined Control Method Using Sparsely Activated Microcontroller for Low-Power, Multiple-Input, Single-Inductor, Multiple-Output DC-DC Converters to Increase Efficiency.
IEEE Trans. Ind. Electron., 2023

2022
A Simple Hardware-Based Fault-Tolerant Method for Cascaded H-Bridge Converters.
IEEE Trans. Ind. Electron., 2022

A Low-Power Logarithmic CMOS Digital-to-Analog Converter for Neural Signal Recording.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT.
J. Circuits Syst. Comput., 2022

2021
A 1.2 GHz jitter-peaking-free Integer-N PLL.
Microelectron. J., 2021

C3S-QVCO: A low phase noise low power super-harmonic coupling QVCO with cross-connected common-source nodes.
Microelectron. J., 2021

BISH-QVCO: A Low-Power, Low-Phase noise Bulk-Injected Super-Harmonic coupling QVCO.
Microelectron. J., 2021

Hardware-Efficient Bartlett Spectral Density Estimator Based on Optimized R2<sup>2</sup>FFT Processor Using CCSSI Method.
J. Circuits Syst. Comput., 2021

Optimal sub-harmonic injection-locked MICS band transmitter for wireless CW-fNIRS systems.
Int. J. Circuit Theory Appl., 2021

A fast settling frequency synthesizer with switched-bandwidth loop filter.
Int. J. Circuit Theory Appl., 2021

Phase noise analysis of the connected-sources parallel quadrature oscillator.
Comput. Electr. Eng., 2021

2020
An O(1) time complexity sorting network for small number of inputs with hardware implementation.
Microprocess. Microsystems, 2020

1/f<sup>3</sup> (Close-in) Phase Noise Reduction by Tail Transistor Flicker Noise Suppression Technique.
J. Circuits Syst. Comput., 2020

A low-power, low-data-rate efficient ADC with hybrid exponential-linear transfer curve for bio-potential recording systems.
Int. J. Circuit Theory Appl., 2020

Control of computer pointer using hand gesture recognition in motion pictures.
CoRR, 2020

2019
A low-power low-noise CMOS bio-potential amplifier for multi-channel neural recording with active DC-rejection and current sharing.
Microelectron. J., 2019

FPGA implementation of an adaptive window size image impulse noise suppression system.
J. Real Time Image Process., 2019

2018
A 60 mV Input Voltage, Process Tolerant Start-Up System for Thermoelectric Energy Harvesting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A low phase noise super-harmonic coupling quadrature VCO using an additional double frequency oscillator.
Microelectron. J., 2018

Pseudo-impulse tail current shaping for phase noise reduction in CMOS LC oscillators.
Microelectron. J., 2018

2017
Phase noise reduction in a CMOS LC cross coupled oscillator using a novel tail current noise second harmonic filtering technique.
Microelectron. J., 2017

2015
A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process.
Int. J. Circuit Theory Appl., 2015

2013
Design of a direct conversion ultra low power ZigBee receiver RF front-end for wireless sensor networks.
Microelectron. J., 2013

2012
A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE.
Microelectron. J., 2012

2011
Digital Compensation Techniques for Frequency-Translating Hybrid Analog-to-Digital Converters.
IEEE Trans. Instrum. Meas., 2011

A 12.5Gb/s active-inductor based transmitter for I/O applications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008
Energy Recovery from High-Frequency Clocks Using DC-DC Converters.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 0.35µm CMOS comparator circuit for high-speed ADC applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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