Salvador Manich
Orcid: 0000-0001-5265-1209
According to our database1,
Salvador Manich
authored at least 30 papers
between 1996 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
2023
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs.
IEEE Access, 2023
2022
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact.
IEEE Access, 2022
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
2017
Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis.
Microelectron. J., 2017
2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
2015
IET Comput. Digit. Tech., 2015
2014
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2014
Interleaved scrambling technique: A novel low-power security layer for cache memories.
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
2010
Proceedings of the 15th European Test Symposium, 2010
2007
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
2004
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
2003
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.
Proceedings of the Integrated Circuit and System Design, 2003
On the selection of efficient arithmetic additive test pattern generators [logic test].
Proceedings of the 8th European Test Workshop, 2003
2002
On High-Quality, Low Energy BIST Preparation at RT-Level.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2000
1999
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1997
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.
Proceedings of the European Design and Test Conference, 1997
1996
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I<sub>DDQ</sub> monitoring.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations.
Proceedings of the 1996 European Design and Test Conference, 1996