Salil Raje

According to our database, Salil Raje authored at least 17 papers between 1993 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2004

Innovate or perish: FPGA physical design.

Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh

Proceedings of the 2004 International Symposium on Physical Design, 2004

What is the right model for programming and using modern FPGAs?

André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.

Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis

Proceedings of the 41th Design Automation Conference, 2004

2003

Multi-Million Gate FPGA Physical Design Challenges.

Maogang Wang, Abhishek Ranjan, Salil Raje

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

An analysis of the wire-load model uncertainty problem.

Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

Overcoming wireload model uncertainty during physical design.

Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje

Proceedings of the 2001 International Symposium on Physical Design, 2001

1999

Scheduling with multiple voltages under resource constraints.

Majid Sarrafzadeh, Salil Raje

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications.

Jun Dong Cho, Salil Raje, Majid Sarrafzadeh

IEEE Trans. Computers, 1998

1997

Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system.

Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan

IEEE Trans. Very Large Scale Integr. Syst., 1997

Scheduling with multiple voltages.

Salil Raje, Majid Sarrafzadeh

Integr., 1997

Observable Time Windows: Verifying High-Level Synthesis Results.

Reinaldo A. Bergamaschi, Salil Raje

IEEE Des. Test Comput., 1997

Generalized resource sharing.

Salil Raje, Reinaldo A. Bergamaschi

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Observable Time Windows: Verifying the Results of High-Level Synthesis.

Reinaldo A. Bergamaschi, Salil Raje

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Variable voltage scheduling.

Salil Raje, Majid Sarrafzadeh

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Constrained Register Allocation in Bus Architectures.

Elof Frank, Salil Raje, Majid Sarrafzadeh

Proceedings of the 32st Conference on Design Automation, 1995

1994

Approximation Algorithm on Multi-Way Maxcut Partitioning.

Jun Dong Cho, Salil Raje, Majid Sarrafzadeh

Proceedings of the Algorithms, 1994

1993

GEM: A Geometric Algorithm for Scheduling.

Salil Raje, Majid Sarrafzadeh

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993