Sajjad Parvin

According to our database, Sajjad Parvin authored at least 14 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Lower the RISC: Designing optical-probing-attack-resistant cores.

Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler

Microprocess. Microsystems, 2024

Hidden Cost of Circuit Design with RFETs.

Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing.

Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing.

Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core.

Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study.

Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques.

Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Efficient Hardware Realizations of Feedforward Artificial Neural Networks.

Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun

CoRR, 2021

A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks.

Sajjad Parvin, Mustafa Altun

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks.

Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks.

Levent Aksoy, Sajjad Parvin, Mohammadreza Esmali Nojehdeh, Mustafa Altun

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates.

Sajjad Parvin, Mustafa Altun

IEEE Access, 2019

Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates.

Sajjad Parvin, Mustafa Altun

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits.

Mustafa Altun, Sajjad Parvin, M. Hüsrev Cilasun

IEEE Access, 2018