Sajid Khan

According to our database, Sajid Khan authored at least 7 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Pass Transistor XOR Gate Based Radiation Hardened RO-PUF.

Syed Farah Naz, Sajid Khan, Ambika Prasad Shah

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2019

An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications.

Sajid Khan, Ambika Prasad Shah, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma

Microelectron. J., 2019

Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network.

Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security.

Sajid Khan, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An Ultra Low Power AES Architecture for IoT.

Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell.

Neha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2018

A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations.

Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar, Raj Singh

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018