Sajid Baloch

According to our database1, Sajid Baloch authored at least 14 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

2020
An Integer Cat Swarm Optimization Approach for Energy and Throughput Efficient MPSoC Design.
Int. J. Comput. Intell. Syst., 2020

2014
Hardware realization of locally normalized cross correlation algorithm.
Proceedings of the 2nd International Conference on Systems and Informatics, 2014

2007
Single event upset hardened embedded domain specific reconfigurable architecture.
PhD thesis, 2007

Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Improved memory strategy for logmap turbo decoders.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Domain-Specific Reconfigurable Array Targeting Discrete Wavelet Transform for System-on-Chip Applications.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays.
Proceedings of the 2004 Design, 2004


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