Saidapet Ramesh

According to our database, Saidapet Ramesh authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Customizing ATPG User-Defined Stresses and Tests To Target Cell-Neighborhood-Bridging Defects.

Stephen Traynor, Saidapet Ramesh, Maryfe Hernandez, Lawrence Herr, Scott Chen

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2023

Targeted Custom High-Voltage Stress Patterns on Automotive Designs.

Saidapet Ramesh, Kristofor Dickson, Akshay Jaiswal, Robert Marchese, Kiran Sunny Thota

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes.

Saidapet Ramesh, Rahul Kalyan, Jesse Yanez, Andreas Glowatz, Maija Ryynänen, Sergej Schwarz

Proceedings of the IEEE International Test Conference, 2023

2021

Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs.

Jorge Corso, Saidapet Ramesh, Kumar Abishek, Ley Teng Tan, Chik Hooi Lew

Proceedings of the IEEE International Test Conference, 2021