Said Belkouch
According to our database1,
Said Belkouch
authored at least 18 papers
between 2007 and 2022.
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Bibliography
2022
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures.
Comput. Electr. Eng., 2022
An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs.
Proceedings of the 3rd IEEE International Conference on Electronics, 2022
2021
An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP.
Microprocess. Microsystems, September, 2021
2020
Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU-GPU platforms.
J. Real Time Image Process., 2020
Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture.
J. Circuits Syst. Comput., 2020
2018
Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection.
Proceedings of the 5th IEEE International Congress on Information Science and Technology, 2018
Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection.
Proceedings of the 4th International Conference on Advanced Technologies for Signal and Image Processing, 2018
2017
VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing.
J. Circuits Syst. Comput., 2017
Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications.
Proceedings of the 2nd international Conference on Big Data, Cloud and Applications, 2017
2016
Efficient architecture for direct 8 × 8 2D DCT computations with earlier zigzag ordering.
Multim. Tools Appl., 2016
Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage.
EURASIP J. Adv. Signal Process., 2016
2015
Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors.
Proceedings of the 15th International Conference on Intelligent Systems Design and Applications, 2015
Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders.
Proceedings of the 12th IEEE/ACS International Conference of Computer Systems and Applications, 2015
2014
Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect.
EURASIP J. Adv. Signal Process., 2014
Proceedings of the 26th International Conference on Microelectronics, 2014
2013
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications.
Multim. Tools Appl., 2013
2009
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007