Sai Prashanth Muralidhara

Affiliations:
  • Pennsylvania State University, University Park, PA, USA


According to our database1, Sai Prashanth Muralidhara authored at least 15 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2012
Reuse distance based performance modeling and workload mapping.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Communication Based Proactive Link Power Management.
Trans. High Perform. Embed. Archit. Compil., 2011

BrickX: building hybrid systems for recursive computations.
SIGMETRICS Perform. Evaluation Rev., 2011

Reducing memory interference in multicore systems via application-aware memory channel partitioning.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Bandwidth Constrained Coordinated HW/SW Prefetching for Multicores.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
Intra-application shared cache partitioning for multithreaded applications.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

Cache topology aware computation mapping for multicores.
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010

Intra-application cache partitioning.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Computation mapping for multi-level storage cache hierarchies.
Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing, 2010

Code Scheduling for Optimizing Parallelism and Data Locality.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

A special-purpose compiler for look-up table and code generation for function evaluation.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Optimizing shared cache behavior of chip multiprocessors.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Dynamic thread and data mapping for NoC based CMPs.
Proceedings of the 46th Design Automation Conference, 2009

Slicing based code parallelization for minimizing inter-processor communication.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Profiler and compiler assisted adaptive I/O prefetching for shared storage caches.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008


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