Sai Manoj Pudukotai Dinakarrao

Orcid: 0000-0002-4417-2387

According to our database1, Sai Manoj Pudukotai Dinakarrao authored at least 155 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

Performance- and Energy-Aware Gait-Based User Authentication With Intermittent Computation for IoT Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024

3DL-PIM: A Look-Up Table Oriented Programmable Processing in Memory Architecture Based on the 3-D Stacked Memory for Data-Intensive Applications.
IEEE Trans. Emerg. Top. Comput., 2024

Optimizing Malware Detection in IoT Networks: Leveraging Resource-Aware Distributed Computing for Enhanced Security.
CoRR, 2024

Empowering Malware Detection Efficiency within Processing-in-Memory Architecture.
CoRR, 2024

Enhancing IoT Malware Detection through Adaptive Model Parallelism and Resource Optimization.
CoRR, 2024

Generative AI-Based Effective Malware Detection for Embedded Computing Systems.
CoRR, 2024

The Emergence of Hardware Fuzzing: A Critical Review of its Significance.
CoRR, 2024

Processing-in-Memory Architecture with Precision-Scaling for Malware Detection.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Reconfigurable Processing-in-Memory Architecture for Data Intensive Applications.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Dynamic Exit Selection for Comprehensive and Energy Efficient Gait-Based User Authentication on IoT Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTs.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Energy Harvesting-Supported Efficient Low-Power ML Processing with Adaptive Checkpointing and Intermittent Computing.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024

Energy Harvesting-assisted Ultra-Low-Power Processing-in-Memory Accelerator for ML Applications.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive Analysis.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

The Fuzz Odyssey: A Survey on Hardware Fuzzing Frameworks for Hardware Design Verification.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Comprehensive Analysis of Consistency and Robustness of Machine Learning Models in Malware Detection.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions.
Proceedings of the International Conference on Compilers, 2024

Resource- and Workload-aware Malware Detection through Distributed Computing in IoT Networks.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Resource- and Workload-Aware Model Parallelism-Inspired Novel Malware Detection for IoT Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Hardware Trojan Detection Using Machine Learning: A Tutorial.
ACM Trans. Embed. Comput. Syst., 2023

CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering.
Inf., 2023

Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization.
IEEE Access, 2023

Securing AI Hardware: Challenges in Detecting and Mitigating Hardware Trojans in ML Accelerators.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Automated Supervised Topic Modeling Framework for Hardware Weaknesses.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory Architecture for Deep Learning Acceleration.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Don't Cross Me! Cross-layer System Security.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Special Session: Mitigating Side-Channel Attacks Through Circuit to Application Layer Approaches.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

Coarse-Grained High-speed Reconfigurable Array-based Approximate Accelerator for Deep Learning Applications.
Proceedings of the 57th Annual Conference on Information Sciences and Systems, 2023

2022
Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications.
IEEE Trans. Parallel Distributed Syst., 2022

Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation.
ACM Trans. Design Autom. Electr. Syst., 2022

A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Imitating Functional Operations for Mitigating Side-Channel Leakage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Guest Editors' Introduction: Special Issue on Benchmarking Machine Learning Systems and Applications.
IEEE Des. Test, 2022

A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms.
IEEE Des. Test, 2022

A Neural Network-based SAT-Resilient Obfuscation Towards Enhanced Logic Locking.
CoRR, 2022

KF-Loc: A Kalman Filter and Machine Learning Integrated Localization System Using Consumer-Grade Millimeter-Wave Hardware.
IEEE Consumer Electron. Mag., 2022

Characterization of AES Implementations on Microprocessor-based IoT Devices.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2022

Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Neuromorphic-Enabled Security for IoT.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Accelerating Adversarial Attack using Process-in-Memory Architecture.
Proceedings of the 18th International Conference on Mobility, Sensing and Networking, 2022

Adaptive-Gravity: A Defense Against Adversarial Samples.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Performance-aware Lightweight Dynamic Early-Exit-based Gait Authentication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

DQN Based Exit Selection in Multi-Exit Deep Neural Networks for Applications Targeting Situation Awareness.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022

Iron-Dome: Securing IoT Networked Systems at Runtime by Network and Device Characteristics to Confine Malware Epidemics.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

RAFeL - Robust and Data-Aware Federated Learning-inspired Malware Detection in Internet-of-Things (IoT) Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware Detection.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Survey of Machine Learning for Electronic Design Automation.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Session details: Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

CR-Spectre: Defense-Aware ROP Injected Code-Reuse Based Dynamic Spectre.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

LOCK&ROLL: deep-learning power side-channel attack mitigation using emerging reconfigurable devices and logic locking.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Silicon validation of LUT-based logic-locked IP cores.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Adaptive Performance Modeling of Data-intensive Workloads for Resource Provisioning in Virtualized Environment.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021

Self-aware power management for multi-core microprocessors.
Sustain. Comput. Informatics Syst., 2021

AWARe-Wi: A jamming-aware reconfigurable wireless interconnection using adversarial learning for multichip systems.
Sustain. Comput. Informatics Syst., 2021

Deep graph transformation for attributed, directed, and signed networks.
Knowl. Inf. Syst., 2021

Deep Graph Learning for Circuit Deobfuscation.
Frontiers Big Data, 2021

Enabling Micro AI for Securing Edge Devices at Hardware Level.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Energy-Efficient and Error-Resilient Cognitive I/O for 3-D-Integrated Manycore Microprocessors.
IEEE Des. Test, 2021

Power Swapper: Approximate Functional Block Assisted Cryptosystem Security.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Ontology-Driven Framework for Trend Analysis of Vulnerabilities and Impacts in IoT Hardware.
Proceedings of the 15th IEEE International Conference on Semantic Computing, 2021

Machine Learning-Assisted Website Fingerprinting Attacks with Side-Channel Information: A Comprehensive Analysis and Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Conditional Classification: A Solution for Computational Energy Reduction.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Can Overclocking Detect Hardware Trojans?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

What Can a Remote Access Hardware Trojan do to a Network-on-Chip?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data Encryption.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Performance-aware Malware Epidemic Confinement in Large-Scale IoT Networks.
Proceedings of the ICC 2021, 2021

Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band Filtering.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Adversarial Attack Mitigation Approaches Using RRAM-Neuromorphic Architectures.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

HMD-Hardener: Adversarially Robust and Efficient Hardware-Assisted Runtime Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

On-device Malware Detection using Performance-Aware and Robust Collaborative Learning.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Demography-aware COVID-19 Confinement with Game Theory.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

uPIM: Performance-aware Online Learning Capable Processing-in-Memory.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A Survey.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning.
IEEE Comput. Archit. Lett., 2020

Cognitive and Scalable Technique for Securing IoT Networks Against Malware Epidemics.
IEEE Access, 2020

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

R2AD: Randomization and Reconstructor-based Adversarial Defense on Deep Neural Network.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

SATConda: SAT to SAT-Hard Clause Translator.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Entropy-Shield: Side-Channel Entropy Maximization for Timing-based Side-Channel Attacks.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Indoor Wireless Localization Using Consumer-Grade 60 GHz Equipment with Machine Learning for Intelligent Material Handling.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

A Comprehensive Review of ML-based Time-Series and Signal Processing Techniques and their Hardware Implementations.
Proceedings of the 11th International Green and Sustainable Computing Workshops, 2020

Evolution of Defenses against Transient-Execution Attacks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Review of In-Memory Computing Architectures for Machine Learning Applications.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

Defense Against on-Chip Trojans Enabling Traffic Analysis Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019
Securing a Wireless Network-on-Chip Against Jamming-Based Denial-of-Service and Eavesdropping Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips.
ACM Trans. Embed. Comput. Syst., 2019

Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management.
ACM J. Emerg. Technol. Comput. Syst., 2019

Computer-aided Arrhythmia Diagnosis with Bio-signal Processing: A Survey of Trends and Techniques.
ACM Comput. Surv., 2019

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
CoRR, 2019

Estimating the Circuit Deobfuscating Runtime based on Graph Deep Learning.
CoRR, 2019

Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Stealthy Malware Detection using RNN-Based Automated Localized Feature Extraction and Classifier.
Proceedings of the 31st IEEE International Conference on Tools with Artificial Intelligence, 2019

RNN-Based Classifier to Detect Stealthy Malware using Localized Features and Complex Symbolic Sequence.
Proceedings of the 18th IEEE International Conference On Machine Learning And Applications, 2019

Deep Multi-attributed Graph Translation with Node-Edge Co-Evolution.
Proceedings of the 2019 IEEE International Conference on Data Mining, 2019

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality.
Proceedings of the International Conference on Computer-Aided Design, 2019

ResCoNN: Resource-Efficient FPGA-Accelerated CNN for Traffic Sign Classification.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

On Custom LUT-based Obfuscation.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Lightweight Node-level Malware Detection and Network-level Malware Confinement in IoT Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Adversarial Attack on Microarchitectural Events based Malware Detectors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MicroArchitectural Events and Image Processing-based Hybrid Approach for Robust Malware Detection.
Proceedings of the 2019 International Conference on Compliers, 2019

SAT to SAT-Hard Clause Translator.
Proceedings of the 2019 International Conference on Compliers, 2019

Sequence-Crafter: Side-Channel Entropy Minimization to Thwart Timing-based Side-Channel Attacks.
Proceedings of the 2019 International Conference on Compliers, 2019

2018
Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

SmartDPM: Machine Learning-Based Dynamic Power Management for Multi-Core Microprocessors.
J. Low Power Electron., 2018

Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration.
IEEE Des. Test, 2018

Customized Machine Learning-Based Hardware-Assisted Malware Detection in Embedded Devices.
Proceedings of the 17th IEEE International Conference On Trust, 2018

A comprehensive memory analysis of data intensive workloads on server class architecture.
Proceedings of the International Symposium on Memory Systems, 2018

Efficient utilization of adversarial training towards robust machine learners and its analysis.
Proceedings of the International Conference on Computer-Aided Design, 2018

ADDHard: Arrhythmia Detection with Digital Hardware by Learning ECG Signal.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A fast and resource efficient FPGA implementation of secret sharing for storage applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Comprehensive assessment of run-time hardware-supported malware detection using general and ensemble learning.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Advances and throwbacks in hardware-assisted security: special session.
Proceedings of the International Conference on Compilers, 2018

Compressive Sensing on Storage Data: An Effective Solution to Alleviate I/0 Bottleneck in Data- Intensive Workloads.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Self-aware sensing and attention-based data collection in Multi-Processor System-on-Chips.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Neural network based ECG anomaly detection on FPGA and trade-off analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory.
IEEE Trans. Computers, 2016

Fully digital write-in scheme for multi-bit memristive storage.
Proceedings of the 13th International Conference on Electrical Engineering, 2016

2015
3D Many-Core Microprocessor Power Management by Space-Time Multiplexing Based Demand-Supply Matching.
IEEE Trans. Computers, 2015

A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller.
IEEE Des. Test, 2015

Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Memristors' Potential for Multi-bit Storage and Pattern Learning.
Proceedings of the 2015 IEEE European Modelling Symposium, 2015

A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation.
Proceedings of the International Symposium on Physical Design, 2013

Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013


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