Sai Lalith Chaitanya Ambatipudi
Orcid: 0000-0001-6001-9748
According to our database1,
Sai Lalith Chaitanya Ambatipudi
authored at least 6 papers
between 2018 and 2020.
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Bibliography
2020
IEEE J. Solid State Circuits, 2020
Proceedings of the European Conference on Optical Communications, 2020
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018